Taiwan Semiconductor Manufacturing Comp. Ltd.

Ping-Kun Wu

Chao-Hsiung Wang

Fu-Liang Yang

Hung-Wei Chen

Sheng-Da Liu

Chang-Yun Chang

Tang-Xuan Zhong

Horng-Huei Tseng

Shau-Lin Shue

Chenming Hu

Hao-Yu Chen

Chine-Gie Lo

Tang-Xuang Zhong

Chang-Yu Chang

A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

Structure for a multiple-gate FET device and a method for its fabrication

An integrated circuit device comprising a partially embedded and encapsulated damascene structure and method for forming the same to improve adhesion to an overlying dielectric layer, the integrated circuit device including a conductive material partially embedded in an opening formed in a dielectric layer; wherein said conductive material is encapsulated with a first barrier layer comprising sidewall and bottom portions and a second barrier layer covering a top portion, said conductive material and first barrier layer sidewall portions extending to a predetermined height above an upper surface of the dielectric layer to form a partially embedded damascene.

Encapsulated damascene with improved overlayer adhesion

A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.

Method for forming a multi-layer seed layer for improved Cu ECP

In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.

CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof

This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.

Semiconductor structure and method for integrating SOI devices and bulk devices

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Hsin-Chu, Taiwan

Ping-Kun Wu