United Microelectronics Corp.

Ping-I Hsieh

Ming-Jui Chen

Chia-Wei Huang

Te-Hsien Hsieh

Cheng-Te Wang

Jing-Yi Lee

Te-Hung Wu

Shih-Ming Kuo

Pei-Ru Tsai

Ting-Cheng Tseng

Chuen Huei Yang

Sheng-Yuan Huang

Yan-Chun Chen

Po-I Lee

A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Method for optimizing an integrated circuit layout design

A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.

Method of optical proximity correction

A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask.

Method for patterning semiconductor structure

A double patterning mask set includes a first mask having a first set of via patterns, and a second mask having a second set of via patterns. The first set of via patterns includes at least two via patterns arranged along a diagonal direction, each of the at least two via patterns has at least a truncated corner. The first set of via patterns and the second set of via patterns are interlacedly arranged along a horizontal direction and a vertical direction.

Double patterning mask set and method of forming thereof

A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output.

Method to determine process window

A method for amending layout patterns is disclosed. First, a layout pattern after an optical proximity correction is provided, which is called an amended pattern. Later, a positive sizing procedure and a negative sizing procedure are respectively performed on the amended pattern to respectively obtain a positive sizing pattern and a negative sizing pattern. Then, the positive sizing pattern and the negative sizing pattern are respectively verified to know whether they are useable. Afterwards, the useable positive sizing pattern and the negative sizing pattern are output for the manufacture of a reticle when they are verified to be useable.

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Tainan, Taiwan

Ping-I Hsieh