United Microelectronics Corp.

Mediatek Corporation

Ping-Hung Chiang

Shih-Yin Hsiao

Chih-Chung Wang

Wen-Fang Lee

Nien-Chung Li

Chia-Ling Wang

Chia-Wen Lu

Ching-Chung Yang

Chang-Po Hsiung

Kai-Kuen Chang

Kuan-Liang Liu

Wei-lun Huang

Ta-Wei Chiu

Shih-Chieh Pu

Chia-Lin Wang

Wei-De Wu

Mao-Ching Chiu

Po-Ying Chen

Hsin-Han Wu

Chun-Ming Kuo

Shih-Chi Shen

Yen-Hui Yeh

Sheng-Hua Yang

Kuan-Lin Liu

Yen-Ping Lin

In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The configuration specifies a bundle size N. Modulation symbols in N consecutive PRBs are precoded with a same precoder. The UE determines whether a precoding condition is true. The precoding condition is that modulation symbols in a first set of resources and a second set of resources are precoded with a same precoder. Each set of the first set of resources and the second set of resources contains N PRBs. When the precoding condition is met: the UE measures reference signals in the second set of resources; the UE determines a channel condition of the first set of resources in consideration of the measurements of the reference signals in the second set of resources.

Inter-bundle channel estimation and synchronization for downlink data reception

A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Manufacturing method of high voltage semiconductor device

A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

Semiconductor structure and fabrication method thereof

A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

Manufacturing method of semiconductor device

Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Semiconductor device and method of fabricating the same

The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

Semiconductor structure and forming method thereof

High voltage semiconductor device and manufacturing method thereof

A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Method of forming transistor with dual spacer

Transistor with dual spacer and forming method thereof

A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

Semiconductor device

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

High-voltage metal-oxide-semiconductor transistor and fabrication method thereof

A communications apparatus and method are provided. The communications method for an apparatus capable of Carrier Aggregation (CA), wherein the apparatus includes a plurality of processing engines and antennas, includes the steps of determining whether the apparatus is configured in a single component carrier for a first group of the antennas, and activating a second group of the antennas when the apparatus is configured in the single component carrier. T the first group of antennas are configured for a first part of the processing engines and the second group of antennas are configured for a second part of the processing engines, and the first part of the processing engines and the second part of the processing engines share a MIMO detector.

Growing community of inventors

Hsinchu, Taiwan

Ping-Hung Chiang