Spansion Llc.

Cypress Semiconductor Corporation

Ping Hou

Eugen Gershon

Hagop A Nazarian

Chih Hsueh

Richard Chen

Michael Allen Van Buskirk

Wiliam Kern

Rex Hsueh

Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

Error correction for flash memory

An accumulative repeat encoder facilitates encoding data written to memory, such that parity data is generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data is stored in memory. During a read operation, a decoder component utilizes the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component is iterative and provides one or more decoding results based on probabilities that symbols or bits comprising the data have correct values. The decoder component analyzes a decoding result and references a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result is determined to represent the original data and is provided as an output.

Low-density parity-check code based error correction for memory device

A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted.

Cache auto-flush in a solid state memory device

Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one ('L1') cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

Efficient memory hierarchy in solid state drive design

Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.

Systems and methods for locating error bits in encoded data

Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error.

Power safe translation table operation in flash memory

Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

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Fremont, CA, United States of America

Ping Hou