Via Technologies, Inc.

Other

Cadence Design Systems, Inc.

Ebay, Incorporated

Nec Electronics Corporation

Ping F Chen

Zhihong Liu

Li Sun

Fang Liu

Lifeng Wu

Wen-Chung Chen

Xi Xi Liu

Tatsang Mak

Chenggang Liu

Jeong Yeol Choi

Boris Prokopenko

Scot Fraser Hamilton

Nobufusa Iwanishi

Yoshiyuki Kawakami

Hirokazu Yonezawa

Alvin Chen

Norio Koike

Jingkun Fang

Wern-Yan Koe

Gang Zhang

Dehai Kong

Chune-Sin Yeh

Glebs Riskovs

Irene Chih-Yiieh Cheng

Roy (Dehai) Kong

Anh DeCroix

Irene (Chih-Yiieh) Cheng

Peter David Copeland

Alvin I-Hsien Chen

Amol Vilas Sane

Hsilin (Stephen) Huang

Methods, systems, and computer programs are presented for optimizing an input publication with augmented content for optimization across multiple types of computing devices. An input publication is analyzed to extract structure and meaning from the input publication to match the input publication with a standardized publication of a standardized publication catalog, the standardized publication having content that is optimized be displayed on a plurality of computing devices. A preview of the input publication is provided with the content from the standardized publication that is optimized be displayed on a particular computing device. A publication corpus is updated to include the input publication with the content from the standardized publication that is optimized be displayed on the particular computing device.

Preview and optimization of publication for target computing device

An input stream of graphics primitives may be converted into to a predetermined output stream of graphics primitives by a processor in a graphics pipeline. The processor recognizes a predetermined sequence pattern in the input stream of graphics primitives to the processor. The processor determines whether the recognized sequence pattern can be converted into the one of the plurality of predetermined output streams of graphics primitives. If so, the processor identifies a number of vertices in the recognized sequence pattern and reorders the vertices into a predetermined output pattern. Thereafter, the processor outputs the predetermined output pattern corresponding to one or more graphics processing components.

Geometry primitive type conversion in a GPU pipeline

The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added. In an exemplary embodiment, only devices with minimum channel length have degraded models constructed. The present invention also allows the degradation of one device parameter to be determined based on an age value derived from another parameter. In yet another aspect, a degraded device is modeled as a fresh device with a voltage source connected to a terminal.

Hot-carrier device degradation modeling and extraction methodologies

A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a first set of switches. The first set of switches is configured to route communications between the root complex device to either a second connection point of the first GPU via a second set of switches or to a first connection point of a second GPU. The second set of switches is coupled to a second connection point of the first GPU. The second set of switches is configured to route communications to and from the second connection point of the first GPU and to either the root complex device via the first set of switches or to a second connection point of the second GPU.

Switching method and system for multiple GPU support

Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.

Method and system for multiple GPU support

The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.

Method and apparatus for modeling devices having different geometries

A method and circuit for allowing direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to selectively test the core logic and user-defined logic.

Direct access logic testing in integrated circuits

An approach for simulating hot carrier effects in an integrated circuit (IC) at the circuit level includes generating a hot carrier library of delay data for each cell in the IC, using the hot carrier library data to generate a set of scaled timing data for the IC and using the scaled timing data with a IC performance simulator to simulate the IC operation. The scaled timing data is based upon the cell delay data and time-based switching activity of each cell in the IC.

Hot carrier effect simulation for integrated circuits

Shuttle article for games comprising a circular plastic base member having a detachable rubber portion on its bottom, a neck portion on its upper surface, and a cone- or tear-shaped plastic chute flaring from the neck portion to an outer diameter at least twice that of the base member. The chute member is divided into thinly webbed plastic sections by eight plastic ribs which taper from the neck to the outer edges of the chute, with one of the sections being removed to provide an opening for achieving improved turn-around characteristics at the perigee and apogee of flight.

Shuttle article for games

Growing community of inventors

San Jose, CA, United States of America

Ping F Chen