Taiwan Semiconductor Manufacturing Comp. Ltd.

Delta Electronics, Inc.

Ping-Chun Yeh

Shao-Chi Yu

Lien-Yao Tsai

Der-Chyang Yeh

Ruey-Hsin Liu

Mingo Liu

A method includes forming a front-end-of-the-line (FEOL) element over a substrate; forming a back-end-of-the-line (BEOL) element over the FEOL element; forming an interconnection structure over the substrate; forming a conductive shielding layer electrically connected to the interconnection structure and vertically overlapping the FEOL element and the BEOL element, wherein the conductive shielding layer is grounded to the substrate through the interconnection structure; and forming a dielectric layer covering the conductive shielding layer.

Device for protecting FEOL element and BEOL element

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.

An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.

Schottky device

A bias circuit is provided for improving linearity of a radio frequency power amplifier. The bias circuit includes a bias transistor having a collector, an emitter, and a base. The collector is connected to a DC voltage source, the emitter is connected to a radio frequency transistor, and the base is connected to a bias voltage source. A capacitor and an inductor are connected in series and are coupled either between the emitter of the bias transistor and ground or between the base of the bias transistor and ground, thereby constructing an LC series-connected resonator circuit. The LC series-connected resonator circuit directly conducts the part of the radio frequency input signal, which is coupled back to the bias transistor, into the ground, thereby improving linearity of the radio frequency power amplifier. Preferably, the LC series-connected resonator circuit is designed to have a resonant frequency, which is equal to a frequency of a second harmonic component of the radio frequency input signal.

Growing community of inventors

Taichung, Taiwan

Ping-Chun Yeh