International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Globalfoundires Inc.

Auriga Innovations, Inc

Ping-Chuan Wang

Ronald G Filippi

Zhijian Yang

Kai D Feng

Wai-Kin Li

Erdem Kaltalioglu

Lijuan Zhang

Kaushik Chanda

Chengwen Pei

Timothy Dooling Sullivan

Chih-Chao Yang

Oleg Gluschenkov

Hanyi Ding

Louis Lu-Chen Hsu

Conal Eugene Murray

Andrew Tae Kim

Kimball M Watson

Andrew Herbert Simon

Griselda Bonilla

Naftali Eliahu Lustig

Thomas M Shaw

Yun-Yu Wang

Vincent James McGahay

Roy Charles Iggulden

Edward William Kiewra

Hazara Singh Rathore

Yunsheng Song

Louis L Hsu

Fen Chen

Stephan Grunow

Paul Stephen McLaughlin

Rajiv V Joshi

Mukta G Farooq

Zhong-Xiang He

Robert Russell Robison

John Anthony Fitzsimmons

John Matthew Safran

Lynne Marie Gignac

Cathryn Jeanne Christiansen

Qizhi Liu

Hariklia Deligianni

Richard Paul Volant

Robert Allen Groves

James J Demarest

Xiaojin Wei

Xu Ouyang

Louis L C Hsu

Anthony K Stamper

Huilong Zhu

Christopher Vincent Jahnes

Bucknell Chapman Webb

Jin Cai

Minhua Lu

Kafai Lai

Louis C Hsu

Panayotis Constantinou Andricacos

Natalie Barbara Feilchenfeld

Kenneth Jay Stein

Thomas J Fleischman

Dan Moy

David Earle Seeger

Ephrem G Gebreselasie

BethAnn Rainey

Jennifer L Lund

Jeffrey P Gambino

Daniel C Edelstein

William R Tonti

Haining S Yang

Takeshi Nogami

Alvin Jose Joseph

Douglas Duane Coolbaugh

Kenneth Parker Rodbell

Paul Stephen Andry

Chandrasekharan Kothandaraman

Herbert Lei Ho

Robert Mark Rassel

Edmund Juris Sprogis

Wu-Song S Huang

Da-Yuan Shih

Xiao Hu Liu

Robert C Wong

Anthony Richard Bonaccio

Junjing Bao

Ebenezer E Eshun

Shahab Siddiqui

Vidhya Ramachandran

Samuel S Choi

Eric D Hunt-Schroeder

Deok-Kee Kim

Chao-Kun Hu

Hongwen Yan

Lin Zhou

Peter James Lindgren

Stephen Arthur St Onge

David R Hanson

Stephen Dale Wyatt

Emmanuel Yashchin

Nicholas A Polomoff

Bradley Alan Orner

Cornelia Kang-I Tsang

Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide structure including a waveguide core. The structure further comprises a silicide layer, a first dielectric layer arranged in a lateral direction between the silicide layer and the waveguide core, and a second dielectric layer positioned over the waveguide core, the silicide layer, and the first dielectric layer. The first dielectric layer comprises a first material having a first thermal conductivity, and the second dielectric layer comprises a second material having a second thermal conductivity that is less than the first thermal conductivity.

Thermo-optic phase shifters

An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Electromigration monitor

An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.

IC structure with interdigitated conductive elements between metal guard structures

A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) includes at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric.

The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.

Mechanically anchored C4 pad and method of forming same

Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Wafer rigidity with reinforcement structure

A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Wafer reinforcement to reduce wafer curvature

Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.

Interconnect structures for a security application

A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Stacked via structure for metal fuse applications

The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator. At least one bitline extending on a top of the plurality of vertical nanowires and in electrical contact therewith; and at least one wordline formed on vertical sidewalls of the plurality of vertical nanowires and separated therefrom by the dielectric material.

Nanowire-based vertical memory cell array having a metal layer interposed between a common back plate and the nanowires

An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.

On-chip randomness generation

Nanowire-based vertical memory cell array having a back plate and nanowire seeds contacting a bit line

High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

High density capacitor structure and method

A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

Inline measurement of through-silicon via depth

Growing community of inventors

Hopewell Junction, NY, United States of America

Ping-Chuan Wang