Cadence Design Systems, Inc.

Sun Microsystems, Inc.

Ping-Chih Wu

Kit Lam Cheong

Thaddeus Clay McCracken

Patrick John Eichenseer

Jong-Chang Lee

Cecile Nghiem

David S Allison

Wei-Jin Dai

Mohamed Soufi

Paul W Kollaritsch

Weibin Ding

Nasser Nouri

Lung-Chun Liu

Thad Clay McCracken

Louis Liu

Yiqun Ding

Disclosed are improved methods, systems, and computer program products for implementing flexible models to perform efficient prototyping of electronic designs, which allows for very efficient analysis of the electronic designs. The flexible models allow many of the existing tools for designing electronics to perform more efficiently.

Method and system for implementing hierarchical prototyping of electronic designs

Disclosed are improved approaches for implementing design entry. An efficient, spread-sheet based representation is provided for both the instances and connections in a design. Visualization techniques provide the user with visual cues, to direct and identify compatible connection points, unconnected instances, and contention situations. Techniques are disclosed to automatically filter the spreadsheet in a variety of ways, to help the user to dynamically hide portions of the design space that are not interesting at a particular time, and thus to improve the efficiency with which they can work.

Method and system for implementing electronic design entry

Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Method and system for conducting design explorations of an integrated circuit

The present invention relates to performing early design for testing (DFT)-aware prototyping of a design. Unlike prior approaches, the improvement analyzes and considers the impact of test structures at a very early stage of the design process. This allows test structures to be considered and addressed in a more efficient iterative and incremental way, which reduces design cycle time and reduces costs.

Performing early DFT-aware prototyping of a design

A system for tracing signals for a cycle-based simulation includes a traced signal and a system resources availability information of the cycle-based simulation, a runtime compiler configured to use the system resources availability information to assign a system resource to trace the traced signal, a logic design used with the system resources availability information to generate a simulation image, a first value of the traced signal generated by execution of a simulation image, and a traced signal buffer configured to store the first value and upload the first value.

System and method for efficiently tracing simulation data in hardware acceleration simulation systems

Growing community of inventors

Cupertino, CA, United States of America

Ping-Chih Wu