United Microelectronics Corp.

Ping-Chia Shih

Chi-Cheng Huang

Hsiang-Chen Lee

Kuo-Lung Li

Wan-Chun Liao

Chun-Sung Huang

Yu-Chun Chang

Chih-Ming Wang

Chia-Wen Wang

Kuei-Ya Chuang

Ssu-Yin Liu

Meng-Chun Chen

Zi-Jun Liu

Chih-Hung Lin

Chih-Hao Pan

Chia-Min Hung

Wen-Peng Hsu

Ling-Hsiu Chou

Chung-Che Huang

Po-Hsien Chen

Wan-Fang Chung

An-Hsiu Cheng

Che-Hao Kuo

Shou-Wei Hsieh

Yau-Kae Sheu

Wen-Lin Wang

Kun-I Chou

Chung-Chin Shih

Ching-Hua Yeh

Hung-Wei Lin

Yi-Chun Teng

Je-Yi Su

Shao-Nung Huang

Wei-Pin Huang

Ming-Che Tsai

Yu-Cheng Wang

Chiao-Lin Yang

Chin-Fu Lin

Chuan-Fu Wang

Chun-Hung Cheng

Yu-Chun Chen

Ya-Sheng Feng

Ko-Chi Chen

Tzu-Yun Chang

Chih-Hung Wang

Ming-Hua Tsai

Hsueh-Chun Hsiao

Shu-Hung Yu

Chih-Yao Wang

Chuang-Hsin Chueh

Chia-Hui Huang

Chih-Yang Hsu

Yuan-Cheng Yang

Chia-Cheng Hsu

I-Hsin Sung

Che Hao Kuo

Cheng-Hua Chou

Po Hsien Chen

Hsuan-Chun Tseng

Chun-Yao Wang

Mu-Jia Liu

Tseng-Fang Dai

Jheng-Jie Huang

Che-Hao Chang

Jhih-Long Lin

Jaw-Jiun Tu

Ke-Chi Chen

Yu-Cheng Yin

A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

Physical unclonable function generator and manufacturing method thereof

A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.

Method for fabricating physically unclonable function device

A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Flash memory cell

The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Semiconductor structure and manufacturing method thereof

Flash memory cell and forming method thereof

A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

Device for generating security key and manufacturing method thereof

A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

Method for fabricating semiconductor structure

Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.

Semiconductor structure and method of forming the same

A semiconductor memory device includes a substrate, having a plurality of cell regions, wherein the cell regions are parallel and extending along a first direction. A plurality of STI structures is disposed in the substrate, extending along the first direction to isolate the cell regions, wherein the STI structures have a uniform height lower than the substrate in the cell regions. A selection gate line is extending along a second direction and crossing over the cell regions and the STI structures. A control gate line is adjacent to the selection gate line in parallel extending along the second direction and also crosses over the cell regions and the STI structures. The selection gate line and the control gate line together form a two-transistor (2T) memory cell.

Semiconductor memory device and fabrication method thereof

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.

Semiconductor device and manufacturing method thereof

A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

Non-volatile memory device with reduced distance between control gate electrode and selecting gate electrode and manufacturing method thereof

A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

Method for fabricating merging semiconductor integrated circuit

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.

Semiconductor structure and method for fabricating the same

The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S) removing the part of the U-shaped ONO structure; (S) removing the photoresist; (S) removing the pad oxide pattern and the top oxide layer; and (S) forming a gate structure.

Method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell

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Tainan, Taiwan

Ping-Chia Shih