Taiwan Semiconductor Manufacturing Comp. Ltd.

Ping-Cheng Li

Po-Wei Liu

Yong-Shiuan Tsair

Wen-Tuo Huang

Hung-Ling Shih

Yu-Ling Hsu

Chia-Sheng Lin

Shih Kuang Yang

Ming-Hsun Tsai

Yen-Hsun Chen

Chia-Ta Hsieh

Tsung-Yu Yang

Yun-Chi Wu

Yu-Chun Chang

Yu-Wen Tseng

Tsung-Hua Yang

Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Strap-cell architecture for embedded memory

Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Device-region layout for embedded flash

Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Control gate strap layout to improve a word line etch process window

A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Semiconductor isolation structure and method of making the same

An apparatus coupled to a chamber for processing extreme ultraviolet radiation includes a gas inlet configured to direct exhaust gases from the chamber into a combustion zone. The combustion zone is configured to flamelessly ignite the exhaust gases. An air inlet is configured to direct a mixture of air and a fuel into the combustion zone. A control valve is configured to change a volume of fluid exhausted from the combustion zone. A controller configured to control the control valve so as to prevent a pressure inside the combustion zone from exceeding a preset pressure value is provided.

Method and apparatus for controlling exhaust pressure for an extreme ultraviolet generation chamber

Growing community of inventors

Kaohsiung, Taiwan

Ping-Cheng Li