Altera Corporation

Xilinx, Inc.

Other

Intel Corporation

Ping-Chen Liu

Thien Le

Andy Louie Lee

Jason R Bergendahl

Asim A Bajwa

Justin Philpott

Steven P Young

Irfan Rahim

Trevor J Bauer

Suresh M Menon

Atul V Ghia

William Bradley Vest

Paul T Sasaki

Arvind Sherigar

Richard G Cliff

Jeffrey T Watt

Srinivas Perisetty

Lin-Shih Liu

Michael G Ahrens

Bee Yee Ng

Leo Min Maung

Eng Ling Ho

Guang Chen

Chiew Siang Wong

Gaik Ming Chan

Jeffery Chow

Ravi Thiruveedhula

Shen Shen Lee

Kenneth V Miu

Siaw Chen Lee

Venu Kondapalli

Systems and methods of the present disclosure may provide efficient power consumption for programmable logic devices based on unused portions of programmable logic. A programmable logic device includes a plurality of programmable logic sectors that implement a circuit design, unused portions of the programmable logic device, and interconnection resources. The interconnection resources include a multiplexer that receives a control signal and that generates an output signal based on the control signal and a driver that receives the output signal and that implements a low-power mode to reduce leakage current.

Systems and methods for low power modes for programmable logic devices

An integrated circuit includes a first voltage decrease detection circuit that has a first comparator circuit that compares a supply voltage in the integrated circuit to a threshold voltage to generate a first detection signal that indicates a decrease in the supply voltage, and a first timestamp storage circuit that stores a first timestamp in response to the first detection signal indicating the decrease. The integrated circuit includes a second voltage decrease detection circuit that has a second comparator circuit that compares the supply voltage to the threshold voltage to generate a second detection signal that indicates the decrease, and a second timestamp storage circuit that stores a second timestamp in response to the second detection signal indicating the decrease. The integrated circuit includes a control circuit that determines a location of a source of the decrease in the integrated circuit based on the first and the second timestamps.

Circuits and methods for detecting decreases in a supply voltage in an integrated circuit

One embodiment relates to a method of controlling supply voltage regulation within an integrated circuit. An external interrupt is sent from an external interaction processing layer to a processor in the integrated circuit. Off-die instructions are generated by the external interaction processing layer and sent to the processor. The off-die instructions are executed by the processor to test and adjust supply voltage regulation within the integrated circuit on a sector-by-sector basis. Another embodiment relates to a method of controlling a supply voltage regulator for a sector of an integrated circuit. Commands are sent by a processor and translated by a sector manager to bits. The bits are loaded into registers so as to set the regulator control circuit to the testing mode send a supply voltage to an analog-to-digital converter. Other embodiments and features are also disclosed.

Apparatus and method of voltage regulation control for integrated circuit

Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations in the memory mode, the configuration ports may be gated off to prevent existing user data from being accessed. Each column of memory cells may be arranged into groups. Each group of memory cells in a column may be connected to a respective local data line, which is connected to a global data line via a switch. The switch may be selectively activated to short the local data line to the global data line. Configured in this hierarchical data line architecture, leakage at the global data line can dramatically be reduced, and the memory cell read margin is improved.

Circuitry for reducing leakage current in configuration memory

An integrated circuit having power supply circuitry configured to generate a temperature dependent power supply voltage is provided. The power supply circuitry may include temperature sensors formed at different regions on the integrated circuit. The power supply circuitry may use a selected one of the temperature sensors to vary the temperature dependent power supply voltage. The power supply circuitry may include voltage clamping circuitry configured to clip the power supply voltage to an upper fixed voltage level when the power supply voltage exceeds a first predetermined threshold and to clip the power supply voltage to a lower fixed voltage level when the power supply voltage falls below a second predetermined threshold. The power supply circuitry may also include voltage overshoot-undershoot protection circuitry configured to keep the temperature dependent power supply voltage within a specified voltage range in the presence of transient perturbations in the temperature dependent power supply voltage.

Temperature dependent power supply circuitry

An integrated circuit with voltage regulator circuitry is provided. The voltage regulator circuitry may include an adaptive bleeder circuit. The adaptive bleeder circuit may include one or more switchable current leaker paths and an associated bleeder control circuit having current sensing circuitry and voltage comparison circuitry. The current sensing circuitry may monitor the amount of current that is being delivered to a load circuit, whereas the voltage comparison circuitry may output control signals that selectively activate one or more of the current leaker paths depending on the monitored current values. Adaptive bleeder circuit configured in this way can help maintain stability of the voltage regulator while minimizing dynamic power consumption.

Integrated circuit voltage regulator with adaptive current bleeder circuit

A voltage regulator is disclosed. The voltage regulator includes an operational amplifier (op-amp) and a voltage trim circuit. The op-amp is operable to receive a reference voltage at a first terminal. The op-amp also includes an output terminal. The voltage trim circuit is coupled between the output terminal and a second terminal of the op-amp. The voltage trim circuit is operable to modify an output voltage to be substantially equivalent with the reference voltage. The modification is performed by selecting an electrical current propagating pathway. An IC and a method to operate the voltage regulator is also disclosed.

Voltage regulator and a method to operate the voltage regulator

A startup circuit to ensure a bandgap reference circuit reliably starts up or recovers from a noise disturbance is provided. The startup circuit incorporates a pull down resistor to detect the bandgap reference circuit being in a disabled state. The startup circuit creates a positive feedback loop to force the bandgap reference circuit out of a disabled state. Consequently, whenever the power supply for the bandgap reference circuit sags or if bandgap output collapses, the output of the bandgap circuit reliably ramps back up to the expected level.

Startup circuit

A field programmable gate array (FPGA) includes a set of monitor circuits adapted to provide indications of process, voltage, and temperature for at least one circuit in the FPGA, and a controller adapted to derive a range of body-bias values for the at least one circuit from the indications of process, voltage, and temperature for the at least one circuit. The FPGA further includes a body-bias generator adapted to provide a body-bias signal to at least one transistor in the at least one circuit. The body-bias signal has a value within the range of body-bias values.

Apparatus for improving performance of field programmable gate arrays and associated methods

A comparator is disclosed. The comparator includes a mirror circuit that is electrically coupled to a first voltage source and a second voltage source. The first voltage source produces a first voltage and the second voltage source produces a second voltage. The comparator also includes a first positive metal oxide semiconductor (PMOS) transistor electrically coupled to the first voltage source and an output terminal. The first PMOS transistor is biased by the mirror circuit. The comparator also includes a first negative metal oxide semiconductor (NMOS) that is electrically coupled to a ground terminal and the output terminal. The first NMOS transistor is also biased by the mirror circuit. An electrical current flowing across the first NMOS transistor is mirrored from an electrical current flowing through the first PMOS transistor. A method to operate the comparator and a comparator system is also disclosed.

Low voltage supply comparator and a method to operate the comparator

Voltage regulator circuitry is provided. The voltage regulator circuitry may contain a drive transistor that is controlled by the output of an operational amplifier. The drive transistor may supply a regulated voltage to a load. The operational amplifier may compare a reference voltage and a feedback signal at its inputs. The operational amplifier may include first and second stages. An adjustable resistor may be provided between the first and second stages. Control circuitry may control the resistance of the adjustable resistor based on the amount of current flowing through the load to ensure stable operation of the voltage regulator circuitry. Overshoot and undershoot detection and compensation circuitry may compensate for overshoot and undershoot in the regulated voltage. Voltage ramp control circuitry may be used to control the ramp rate of the regulated voltage.

Voltage regulator circuitry with adaptive compensation

Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.

Memory elements with voltage overstress protection

A low dropout (LDO) voltage regulator with unconditional frequency compensation is presented. The low dropout voltage regulator is implemented using a two-stage operational amplifier. The first stage amplifier has two input transistors, each of which is connected to a diode-connected transistor. A transistor is connected in parallel to the diode-connected transistors to increase the gain of the first stage amplifier. The LDO voltage regulator has a compensation capacitance input between the first stage amplifier and the second stage amplifier and a voltage on the compensation capacitance input adjusts the current through the diode-connected transistors, as well as the gain of the first stage amplifier. The second stage amplifier receives output from the first stage amplifier, and a compensation capacitor is connected between the compensation capacitance input of the operational amplifier and the output node of the LDO voltage regulator.

Unconditional frequency compensation technique on-chip low dropout voltage regulator

A charge pump circuit is provided that has a controllable ramp rate. The charge pump circuit may receive a control signal from a control circuit. The control signal may be asserted by the control circuit to turn on the charge pump circuit. When the charge pump circuit is turned on, the charge pump circuit produces an output voltage. The output voltage ramps up from an initial value to a desired target value. During the ramp up process, a ramp rate regulation circuit monitors the output voltage and ensures that the ramp rate does not exceed a desired maximum value. A capacitor may be charged at a desired ramp rate to use as a time-varying reference voltage. A feedback circuit may be used to maintain the output voltage at the desired target value once the ramp-up process is complete.

Charge pump with ramp rate control

Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

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Fremont, CA, United States of America

Ping-Chen Liu