Samsung Electronics Co., Ltd.

Pil-Soon Park

Jun-Young Jeon

Soo-In Cho

Kyung-woo Kang

A data output buffer control circuit for a semiconductor memory device assures a column address setup time and a valid data setup time in EDO mode by eliminating short glitches in the data output buffer. The circuit assures the column address setup time by disabling the data output buffer for a predetermined period of time after an address transition, regardless of the state of a column address strobe signal. The circuit assures the setup time for valid data by sensing when the address is set up relative to when the column address strobe signal is activated, and then enabling the data output buffer so as to maintain invalid data in the data output buffer long enough to prevent a short glitch in the data output buffer if the column address is set up before the column address strobe signal is activated. The circuit includes a pulse generator for generating a pulse signal each time it senses a column address transition, and a latch circuit for combining the pulse signal with the column address strobe signal so as to generate a buffer control signal for enabling and disabling the data output buffer.

Data output buffer control circuit for a semiconductor memory device

A method and system for arranging power lines of a semiconductor memory device in order to prevent cracking of the power lines and to reduce resistance of the power lines without the provision of slits in the power lines. A first metal and a second metal for a first power line are connected to each other by contacting the first metal with the second metal; a first metal and a second metal for a second power line are also connected to each other by contacting the first metal with the second metal; the first metal for the first power line and the first metal for the second power line are arranged adjacent to each other; the second metal for the first power line and the second power line for the second power line are also arranged adjacent to each other; and the second metal of the first power line partially overlaps both the first metal for the first power line and the first metal for the second power line. No slits are provided between the first metals for the first and second power lines and the second metals therefor.

Multiple power line arrangement for a semiconductor memory device

An integrated circuit output driver system includes a first power line channel extending along the integrated circuit. The first power line channel includes a first power supply voltage line and a first ground voltage line. A second power line channel also extends along the integrated circuit and is spaced apart from the first power line channel. The second power line channel includes a second power supply voltage line and a second ground voltage line. A plurality of output drivers are located between the first and second spaced apart power line channels. Each output driver includes an output node, a pull-up circuit which pulls up the output node in response to a pull-up input signal, and a pull-down circuit which pulls down the output node in response to a pull-down input signal. The power supply and ground voltage connections for alternating output drivers are supplied by the first power supply voltage line and the second ground voltage line, and the second power supply voltage line and the first ground voltage line respectively. Switching noise on the power lines may thereby be reduced.

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Suwon, South Korea

Pil-Soon Park