Amkor Technology, Inc.

Amkor Technology Singapore Holding Pte. Ltd.

Pil Je Sung

Jong Sik Paek

Doo Hyun Park

Seong Min Seo

Yong Min Song

Seo Yeon Ahn

Sung Geun Kang

Wang Gu Lee

Eun Young Lee

Won Chul Do

Do Hyung Kim

In Bae Park

Jin Hee Park

Chang Min Lee

Seung Chul Han

Young Rae Kim

SungGeun Kang

Garry Pycroft

John Merrill Nickelsen, Jr

Joo Hyun Kim

Hui Tae Kim

A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

Semiconductor device and manufacturing method thereof

A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or more mounted components prior to additional assembly.

Disclosed are a semiconductor device and a manufacturing method thereof, which can achieve miniaturization and improvement in the integration level by forming a substrate using a pattern layer implemented on a wafer in a semiconductor fabrication (FAB) process. In one exemplified embodiment, the manufacturing method of the semiconductor device includes preparing a first semiconductor die including a plurality of through electrodes and a plurality of first conductive pillars, mounting the first semiconductor die to connect the first conductive pillars to the pattern layer provided on a wafer, forming a first encapsulant to cover the pattern layer and the first semiconductor die, mounting a second semiconductor die to electrically connect second conductive pillars provided in the second semiconductor die to the plurality of through electrodes exposed to a second surface of the first semiconductor die, and removing the wafer from a first surface of the pattern layer.

A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.

Semiconductor device utilizing redistribution layers to couple stacked die

A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.

Semiconductor device utilzing redistribution layers to couple stacked die

In accordance with the present invention, there is provided a CPV package which comprises a leadframe assembly, such leadframe assembly including multiple frames stacked on top of each other. A top frame of the leadframe assembly provides the electrical interconnect between the top or front surface of the receiver die and the bypass diode required to complete the circuit. The top frame also provides hook up wire interconnect pads for the completed CPV package. An exposed bottom surface of a bottom frame of the leadframe assembly defines a heat spreader which assists in thermal management. The fabrication of the CPV package to include multiple frames stacked on top of each other provides high thermal dissipation and high voltage isolation, while at the same providing a high level of reliability with a comparatively low manufacturing cost.

Concentrated photovoltaic receiver package with stacked internal support features

Growing community of inventors

Seoul, South Korea

Pil Je Sung