Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Pietro Montanini

Marco Ferrera

Benedetto Vigna

Paolo Ferrari

Marta Mottura

Riccardo Depetro

Laura Maria Castoldi

Ilaria Gelmi

Giuseppe Croce

Giuseppe Ammendola

Marco Annese

Flavio Francesco Villa

Ubaldo Mastromatteo

Gabriele Barlocchi

Fabrizio Fausto Renzo Toia

Andrea Pallotta

Michele Palmieri

Luca Zanotti

Mario Foroni

Lucia Zullino

Paolo Vergani

Francesco Martini

Anna Ponza

Giovanna Germani

Paolo Riboli

Mottura Marta

Aurea Cuccia

The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Process for etching trenches in an integrated optical device

An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow.

Deep contacts of integrated electronic devices based on regions implanted through trenches

A method for manufacturing an integrated electronic device. The method includes providing an SOI substrate having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor starting layer on the insulating layer; epitaxially growing the starting layer to obtain a semiconductor active layer on the insulating layer for integrating components of the device, and forming at least one contact trench extending from an exposed surface of the starting layer to the semiconductor substrate before the step of epitaxially growing the starting layer, wherein each contact trench clears a corresponding portion of the starting layer, of the insulating layer and of the semiconductor substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling the at least one contact trench with semiconductor material.

SOI device with contact trenches formed during epitaxial growing

A method of fabricating a wafer-size photovoltaic cell module includes defining an integrated cellular structure of a light converting monolateral or bilateral junction diode in an epitaxially grown detachable layer including a first deposited metal current collecting terminal of the diode. The method also includes laminating onto the surface of the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions. The method further includes immersing the wafer in a hydrofluoric acid solution causing detachment of the epitaxially grown silicon layer laminated with the film, and polishing the surface of separation of the detached epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a temperature tolerable by the film.

Method of fabrication of plastic film supported single crystal silicon photovoltaic cell structure

An electronic device is proposed. The device is integrated in a chip including at least one stacked layer having a front surface and a rear surface opposite the front surface, the device including: an insulating trench insulating an active region of the chip, the insulating trench having a section across each plane parallel to the front surface extending along a longitudinal line, and a front-rear contact electrically contacting the front surface to the rear surface in the active region, wherein the section of the insulating trench has a non-uniform width along the longitudinal line, and/or the device further includes at least one further insulating trench within the active region.

Front-rear contacts of electronics devices with induced defects to increase conductivity thereof

A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.

Process for manufacturing high-sensitivity accelerometric and gyroscopic integrated sensors, and sensor thus produced

An insulated-gate transistor includes a semiconductor layer of a first conductivity type, an insulated gate comprising a trench gate extending into the semiconductor layer, a source and a drain regions of a second conductivity type formed in the semiconductor layer at respective sides of the trench gate, wherein each one of the source and drain regions includes a first doped region, having a first dopant concentration, formed in the semiconductor layer adjacent to the trench gate, said first dopant concentration being such that a breakdown voltage of the junction formed by the first doped region and the semiconductor layer is higher than a predetermined breakdown voltage, and a second doped region, having a second dopant concentration higher than the first dopant concentration, said second doped region being formed in the first doped region and being spaced apart from the trench gate, the second dopant concentration being adapted to form a non-rectifying contact for electrically contacting the first doped region.

Folded-gate MOS transistor

A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages, in order to free the portions.

Process for the singulation of integrated devices in thin semiconductor chips

A method manufactures a vertical-gate MOS transistor integrated in a semiconductor chip having a main surface. The method includes: forming a trench gate extending into the chip from the main surface to a gate depth, by forming a control gate and an insulation layer for insulating the control gate from the chip. Forming the trench gate includes: forming a trench extending into the chip from the main surface to a protection depth less than the gate depth, the trench having a lateral wall and a bottom wall with an edge portion of the lateral wall extending from the main surface being inclined outwardly with respect to the remaining portion of the lateral wall; forming a first auxiliary insulation layer in the trench; removing a bottom wall of the first auxiliary insulation layer; extending the trench to the gate depth; and forming a second auxiliary insulation layer in the trench.

Method for manufacturing a vertical-gate MOS transistor with countersunk trench-gate

A packaging structure for optoelectronic components is formed by a first body, of semiconductor material, and a second body, of semiconductor material, fixed to a first face of said first body. A through window is formed in the second body and exposes a portion of the first face of the first body, whereon at least one optoelectronic component is fixed. Through connection regions extend through the first body and are in electrical contact with the optoelectronic component. The through connection regions are insulated from the rest of the first body via through insulation regions. Contact regions are arranged on the bottom face of the first body and are connected to said optoelectronic component via the through connection regions.

Method for manufacturing encapsulated opto-electronic devices and encapsulated device thus obtained

Method for manufacturing an SOI wafer. On a monocrystalline silicon wafer, forming protective regions having the shape of an overturned U, made of an oxidation resistant material, the protective regions covering first wafer portions. Forming deep trenches in the wafer which extend between, and laterally delimit the first wafer portions, completely oxidizing the first wafer portions except their upper areas which are covered by the protective regions, to form at least one continuous region of covered oxide overlaid by the non-oxidized upper portions. Removing the protective regions, and epitaxially growing a crystalline semiconductor material layer from the non-oxidized upper portions.

Method for manufacturing an SOI wafer

A method for the formation of a region of silicon dioxide on a substrate of monocrystalline silicon. The epitaxial growth of a silicon layer, the opening of holes in the silicon layer above the silicon dioxide region, and the removal of the silicon dioxide which constitutes the region by means of chemical attack through the holes until a silicon diaphragm, attached to the substrate along the edges and separated therefrom by a space, is produced. In order to form an absolute pressure microsensor, the space has to be sealed. To do this, the method provides for the holes to have diameters smaller than the thickness of the diaphragm and to be closed by the formation of a silicon dioxide layer by vapor-phase deposition at atmospheric pressure.

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Milan, Italy

Pietro Montanini