International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Samsung Electronics Co., Ltd.

Pietro Montanini

Ruilong Xie

Kangguo Cheng

Nicolas J Loubet

Julien Frougier

Balasubramanian Pranatharthiharan

Andrew Mark Greene

Steven J Bentley

Tenko Yamashita

John H Zhang

Eric R Miller

Christopher Michael Prindle

Shogo Mochizuki

Oleg Gluschenkov

Hemanth Jagannathan

Sivananda K Kanakasabapathy

Wenyu Xu

Soon-Cheon Seo

Hong He

Gauri V Karve

Cheng Chi

Robin Hsin Kuo Chao

Veeraraghavan S Basker

Junli Wang

Chen Zhang

Ruqiang Bao

Zhenxing Bi

Jingyun Zhang

Hiroaki Niimi

Siva P Adusumilli

John Ryan Sporre

Henry K Utomo

Ju Youn Kim

Brett H Engel

Roderick Miller

Raymond Joy

Robinhsinku Chao

Gerald Leake, Jr

Marta Mottura

A semiconductor structure comprises a substrate defining a first axis and a second axis in orthogonal relation to the first axis, first and second nanosheet stacks disposed on the substrate, a gate structure on each of the first and second nanosheet stacks, a source/drain region adjacent each of the first and second nanosheet stacks, a wrap-around contact disposed about each source/drain region and an isolator pillar disposed between the wrap-around contacts.

Wrap-around contact for nanosheet device

A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.

Hybrid complementary field effect transistor device

A semiconductor device structure and a method for fabricating the semiconductor device structure are disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin.

Vertical field-effect transistor late gate recess process with improved inter-layer dielectric protection

A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.

Nanosheet transistor device with bottom isolation

Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.

Robust low-k bottom spacer for VFET

VTFET devices with bottom source and drain extensions are provided. In one aspect, a method of forming a VTFET device includes: patterning vertical fin channels in a substrate; forming sidewall spacers along the vertical fin channels having a liner and a spacer layer; forming recesses at a base of the vertical fin channels; indenting the liner; annealing the substrate under conditions sufficient to reshape the recesses; forming bottom source and drains in the recesses; forming bottom source and drain extensions in the substrate adjacent to the bottom source and drains; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers alongside the vertical fin channels; forming top spacers over the gate stacks; and forming top source and drains at tops of the vertical fin channels. A VTFET device by the method having bottom source and drain extensions is also provided.

Vertical transport FET with bottom source and drain extensions

A method for forming a semiconductor device is disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin. A novel semiconductor device structure is also disclosed.

A semiconductor device includes a plurality of nano sheet stacks disposed above a substrate. Each nanosheet stack has a first nanosheet and a first sacrificial layer, the first nanosheet and the first sacrificial layer each include a first end and a second end. The first end and the second end of the first sacrificial layer are recessed from the first and second ends of the first nanosheet. Each nanosheet stack has a bottom sacrificial layer formed on top of the substrate. The bottom sacrificial layer has a first end and a second end, which are recessed from the first and second ends of the first nanosheet. The semiconductor also has a source or drain (S/D) structures formed in contact with the first end and the second end of the first nanosheet. The S/D structures are isolated from the substrate by the bottom sacrificial layer.

Nanosheet transistor with fully isolated source and drain regions and spacer pinch off

FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

Utilizing multilayer gate spacer to reduce erosion of semiconductor Fin during spacer patterning

Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.

Sub-thermal switching slope vertical field effect transistor with dual-gate feedback loop mechanism

Embodiments of the present invention are directed to techniques for removing epitaxy defect regions (or nodules) from a semiconductor structure. In a non-limiting embodiment of the invention, a sacrificial gate is formed over a channel region of a fin. The sacrificial gate can include a gate hard mask and a spacer. A source or drain region is formed adjacent to the channel region, resulting in a defect region being formed on a surface of the gate hard mask or the spacer. An organic planarization layer (OPL) is formed on a surface of the source or drain region and the defect region is removed.

Removal of epitaxy defects in transistors

A semiconductor device is fabricated with a first layer of a first sacrificial material deposited over a surface of a substrate. A first set of layers of a second sacrificial material and a second set of layers of a channel material are deposited over the first layer. A liner is deposited in a first recess, which exposes a first connection end of a layer in the second set, where the first recess reaches into the substrate for at least a fraction of a total depth of the substrate. An insulator material is filled in the first recess and etched up to a stop depth, stopping the etching at a height above the surface of the substrate. The liner is removed from at least the first connection end of the layer in the second set. An electrical connection is formed with a source/drain structure using the first connection end.

Dielectric isolation in gate-all-around devices

Growing community of inventors

Albany, NY, United States of America

Pietro Montanini