Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Sgs Microelettronica Spa

Sgsates Componenti Elettronici S.p.a.

Gs Microelettronica S.p.a.

Pietro Erratico

Claudio Diazzi

Carlo Cini

Pietro Consiglio

Flavio Francesco Villa

Gabriele Barlocchi

Pietro Corona

Enrico M Ravanelli

Silvano Coccetti

Antonio Andreini

Enrico Sacchi

Rinaldo Castello

Livio Baldi

Luciano Tomasini

Pietro Menniti

Mauro Merlo

Stefano Manzini

Ferdinando Lari

Valerio Borghese

The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45&#xb0; with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

Process for forming a buried cavity in a semiconductor material wafer and a buried cavity

An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Integrated structure

The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45&deg; with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.

A varactor has a gate region, first and second biasing regions of N type embedded in a well, and first and second extraction regions of P type, forming a pair of PN junctions with the well. The PN junctions are inversely biased and extract charge accumulating in the well, below the gate region, when the gate region is biased to a lower voltage than a predetermined threshold value.

Varactor, in particular for radio-frequency transceivers

Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.

Device for limiting the working voltage for mechanical switches in

A substrate insulation device includes power supply terminals which are connected to a terminal of an active integrated element which has, with respect to a substrate on which it is defined, at least one reverse-biased junction.

Substrate insulation device

A circuit for synthesizing an impedance associated with a telephone subscriber's circuit connected to a two-wire telephone line is described. The circuit of the invention is adapted to synthesize a complex impedance which can function both as a termination impedance and a balance impedance. The termination impedance utilizes a positive feedback loop structure having a loop gain which is at all times less than unity. The circuit that implements both the termination and balance impedances with sidetone suppression is also described. Each of the embodiments is realizable with a single external component consisting of a resistor.

Circuit for the implementation of an impedance for a telephone speech

Device for limiting the working voltage mechanical switches in telephony

An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.

Circuit with diode-protected emitter resistors

An improved planarity when forming contact plugs by a blanket CVD deposition of a metallic matrix layer followed by etchback is achieved by performing a first etchback step to expose the surface of the dielectric material underlying the filling metal layer, while masking the top of the metal plugs with resist caps. The resist caps are formed using a mask derived by field inversion and enlargement from the actual contact mask used for defining the contact areas. With the resist caps covering the contact plugs, the filling metallic material is overetched to eliminate residues along with discontinuities from the planarity of the surface, while shielding the top of the plugs from the overetch. The masked overetch is preferably conducted under conditions of reduced anisotropy and increased selectivity in respect to the first etchback step.

Method for formation of contact plugs utilizing etchback

An amplifier stage with variable gain dependent on the anode voltage is interposed between a ramp generator having constant amplitude ramp output voltage and the vertical deflection stage in such a manner as to vary the input voltage of said vertical deflection stage in accordance with anode voltage variations. In such a manner the vertical deflection current varies correspondingly.

Control circuit with compensation of the anode voltage variation for

A low noise, high thermal stability attenuator of the integratable type is disclosed. The attenuator comprises a fixed network of resistive elements, having a plurality of outputs each at a different attenuation level, and a switched amplifier receiving at its input such different attenuation outputs, as well as a control signal which specifies which of the amplifier inputs is to be output. Advantageously, this attenuator may be implemented in several stages, each having different attenuation ranges or steps.

Low noise, high thermal stability attenuator of the integratable type

A monolithically integrable high-efficiency control circuit for the switching of transistors includes a first transistor whose base terminal is connected to a source of switching signals. A second transistor whose base is connected to a current generator, drives a third transistor which connected in series with the first transistor such that the first and third transistors are connected between two terminals of a supply voltage generator. The emitter terminal of the third transistor forms an output terminal of the control circuit and is connected to the collector terminal of the first transistor by means of a parallel connected diode and a resistor combination. The circuit also includes a fourth transistor, whose base terminal is connected through a resistor to the base terminal of the third transistor and whose collector and emitter terminals are respectively connected to the base terminal of the second transistor and to the collector terminal of the first transistor.

Monolithically integratable high-efficiency control circuit for

In an audio switching power amplifier, muting apparatus provided for eliminating noise signals associated with turn-on and turn-off operations of the apparatus is disclosed. The muting apparatus disables the output power amplifiers and controls signal levels at various positions in the power amplifier to reduce transient conditions. Control apparatus applies the muting signals to the power amplifier during a predetermined period during start-up of the amplifier and applies the muting conditions immediately upon the turning off of power to the power amplifier.

Apparatus and method for muting an output signal in a switching amplifier

This operational amplifier has an output range comprised between values adjustable as desired and includes a differential input stage and an output gain stage, and two additional differential stages supplied at one input with the output voltage of the operational amplifier and at the other input each with a reference voltage representing either the upper limit or the lower limit of the sought range. The outputs of the two additional differential stages are connected to the input stage of the operational amplifier such as not to interfere with the latter when the output voltage of the operational amplifier is comprised between the range limits and to allow switching off and functional substitution of the input stage for either differential stage when the operational amplifier output is equal to the reference voltage of this differential stage, so as to hold that reference voltage at the operational amplifier output regardless of the signal at the input to the operational amplifier.

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Milan, Italy

Pietro Erratico