Meta Platforms Technologies, LLC

Pietro Caragiulo

Daniel Henry Morris

Vivek Venkatesan

Hadi Asgharimoghaddam

Ahmad Abdel Rauof Samih

Vamshi Krishna Lakkaraju

A headset includes a camera a 3D stacked memory configured to store image data captured by the camera, and a System-on-Chip (SoC) configured to process the image data stored in the 3D stacked memory. The 3D stacked memory includes a plurality of first drivers/receivers and a plurality of memory banks that are accessible in parallel. Each memory bank is accessible via a corresponding first driver/receiver. The SoC includes a memory controller with a plurality of second drivers/receivers. The plurality of the second drivers/receivers of the SoC are respectively connected to the plurality of the first drivers/receivers of the 3D stacked memory by a plurality of channels. The SoC and the 3D stacked memory are vertically stacked together. The plurality of the memory banks include at least eight memory banks.

Stacked 3D memory architecture for power optimization

Described are techniques for generating a supply voltage for an SRAM array using power switching logic. The power switching logic can generate the supply voltage using a first supply rail (supplying a higher voltage) during an active state and using a second supply rail (supplying a lower voltage) during a deep retention state. In some examples, a sensing and recovery (SR) unit is provided to sense a decrease in the second voltage, for instance, during the deep retention state. The SR unit can generate an additional voltage that modifies the supply voltage to be higher than the decreased second voltage, thereby reducing droop and/or noise in the second supply rail. The power switching logic, SR unit, and SRAM array can be co-located or distributed across a computer system. For instance, the power switching logic, SR unit, and SRAM array can be embedded within a System on Chip integrated circuit.

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Palo Alto, CA, United States of America

Pietro Caragiulo