Infineon Technologies Ag

Intel Deutschland Gmbh

Pietro Brenner

Edmund Götz

Saqib Kaleem

Walter Hartner

Martin Dechant

Jonas Eric Sebastian Fritzin

Julian Winfried Kaiser

A device includes a high frequency chip and a dielectric material arranged between a first area radiating an electromagnetic interference signal in a first frequency range between 1 GHz and 1 THz and a second area receiving the electromagnetic interference signal. An attenuation of the dielectric material is more than 5 dB/cm at least in a subrange of the first frequency range.

High frequency devices including attenuating dielectric materials

A device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip. The device includes an external connection element configured to provide a first coax-like electrical connection between the device and a printed circuit board, wherein the first coax-like electrical connection includes a section extending in a direction vertical to the main surface of the semiconductor chip. The device further includes an electrical redistribution layer arranged over the main surface of the semiconductor chip and configured to provide a second coax-like electrical connection between the electrical contact of the semiconductor chip and the external connection element, wherein the second coax-like electrical connection includes a section extending in a direction parallel to the main surface of the semiconductor chip.

Devices including coax-like electrical connections and methods for manufacturing thereof

A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

Circuit arrangement with interference protection

The invention proposes a semiconductor configuration having a substrate, which has at least one component integrated therein. The substrate has a first main side with a metalization. At least parts of the metalization are underlaid with an insulation layer located in the substrate. By virtue of the fact that the insulation layer is realized in the form of a trench lattice, it is possible to reduce parasitic capacitances and undesirable signal power losses in the case of high-frequency signals.

Growing community of inventors

Edersberg, Germany

Pietro Brenner