Koninklijke Philips Corporation N.v.

Nxp B.v.

U.S. Philips Corporation

Entropic Communications, Inc.

Pieter Van Der Wolf

Abraham Karel Riemens

Josephus Theodorus Johannes Van Eijndhoven

Om Prakash Gangwal

Jan-Willem Van De Waerdt

Martijn Rutten

Evert-Jan Daniël Pol

Johannes Boonstra

Kornelis A Vissers

Pieter Struik

A cache management policy is provided, comprising a method for writing back to a memory () a data element set () stored in a cache (). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cache for some applications, especially for video applications. The method comprises determining that each one of the multiple data elements has been updated through at least one write request; marking the data element set as a write-back candidate, in dependency on said determination; and writing the write-back candidate to the memory.

Cache management policy and corresponding device

The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H, H, H), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).

Data processing system

Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry () to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory () are used. The first buffer memory () is coupled to the signal processing circuitry via a shareable channel () such as an external IC terminals, but the processing circuitry does not use the shareable channel () to access the second buffer memory (). The second video processing function reads frame data from first and second ones of the frames selectively from the first and second buffer memory () respectively. The second ones of the frames occur in the same temporal order in both the input and output sequence. The first ones of the frames contain at least all particular frames whose position relative to the second ones of the frames in the output sequence differs from the position of the particular frames relative to the second ones of the frames in the input sequence.

Video processing circuit and method of video processing

Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.

Data processing system having multiple processors and a communications means in a data processing system

The data processor contains a memory and a data prefetch unit. The data prefetch unit contains a respective FIFO queue for storing prefetched data from each of a number of address streams respectively. The data prefetch unit uses programmable information to generate addresses from a plurality of address streams and prefetches data from addresses successively addressed by a present address for the data stream in response to progress of execution of a program by the processor. The processor has an instruction which causes the data prefetch unit to extract an oldest data from the FIFO queue for an address stream and which causes the data processor to use the oldest data in the manner of operand data of the instruction.

Data processor

The processing circuit contains a cache management unit which keeps information about a stream of addresses among addresses accessed by the processor. The cache management unit updates a current address for the stream in response to progress of execution of the program. The cache management unit is make selected storage locations in the cache memory available for reuse, a storage location in the cache memory which is in use for the data corresponding to the particular address being made available for reuse dependent on a position of the particular address relative to the current address.

Data processing circuit with cache memory and cache management unit for arranging selected storage location in the cache memory for reuse dependent on a position of particular address relative to current address

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Eindhoven, Netherlands

Pieter Van Der Wolf