Stichting Imec Nederland

Imec

Pieter Harpe

Ming Ding

Hanyue Li

Jiawei Xu

Martijn Timmermans

Example embodiments relate to systems and methods for analog-to-digital signal conversion. One embodiment includes a system for analog-to-digital signal conversion. The system includes an analog input signal. The system also includes a digital-to-analog converter configured to generate a reference signal. Further, the system includes an amplifier configured to amplify an error signal that includes a difference between the analog input signal and the reference signal. Additionally, the system includes a level-crossing based sampling circuit that includes a first comparator configured to compare the error signal with respect to a first reference level, and a second comparator configured to compare the error signal with respect to a second reference level, thereby generating event-based reset signals corresponding to a plurality of sampling instances in order to reset the digital-to-analog converter. Yet further, the system includes a trigger circuit configured to generate reset signals asynchronous to the event-based reset signals.

System and method for analog-to-digital signal conversion

The present disclosure is directed to an impedance spectroscopy system for bio-impedance measurement. The impedance spectroscopy system includes a signal generator configured to generate a signal with a broadband frequency spectrum and to generate an analog injection current from the signal with the broadband frequency spectrum. The analog injection current has a high pass frequency characteristic. The impedance spectroscopy system also includes an amplifier configured to measure a voltage signal in response to the analog injection current and to simultaneously measure a biopotential signal. Further, the impedance spectroscopy system includes a processor configured to analyze the voltage signal to derive a bio-impedance spectrum as well to derive further information from the biopotential signal.

Bio-impedance spectroscopy system and method for bio-impedance measurement

A method of offset calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V), detecting if a binary code determined from the analog input signal (V) matches at least one trigger code, using at least one setting code to determine a calibration bit (B*; B*), analyzing a bit of the digital signal (C) and the calibration bit (B*; B*), determining an indication of a presence of offset error, and calibrating the offset error. As the determination of the calibration bit (B*; B*) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and thus can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Method of offset calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter

A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V), detecting if a binary code determined from the analog input signal (V) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*) and a calibration bit (B*), analyzing a least significant bit of the digital signal (C) and the calibration bit (B*), determining an indication of a presence of gain error in the gain module, and calibrating the gain error. As the determination of the calibration bit (B*) requires only one additional comparison, as compared to normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Method of gain calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter

A method of DAC mismatch calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V), detecting if a binary code determined from the analog input signal (V) matches at least one trigger code, using at least one setting code to determine a calibration residue signal (V*) and a calibration bit (B*), analyzing a least significant bit of the digital signal (C) and the calibration bit (B*), determining an indication of a presence of DAC mismatch, and calibrating the DAC mismatch. As the determination of the calibration bit (B*) requires only one additional comparison, when compared to the normal operation, the normal operation does not need to be interrupted. Therefore, the calibration can be done in the background and, as such, can be performed frequently thereby taking into account time-varying changes due to environmental effects.

Method of digital-to-analog converter mismatch calibration in a successive approximation register analog-to-digital converter and a successive approximation register analog-to-digital converter

A method includes sampling an input voltage signal applied to an ADC, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining in a search logic block a digital code representation for the comparison result. The method may also include performing a calibration by: performing an additional cycle, wherein a last comparison carried out for determining a least significant bit of the digital code representation is repeated with a second comparator resolution mode different from a first comparator resolution mode, so obtaining an additional comparison; determining from a difference between results of the additional comparison and the last comparison a sign of a comparator offset error between the comparator resolution modes; and tuning, in accordance with a sign of the comparator offset error, a programmable capacitor connected at an input of the comparator, thereby inducing a voltage step to counteract the comparator offset error.

Circuit and method for comparator offset error detection and correction in an ADC

A method comprises sampling an input voltage signal, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining an (N+1) bit code representation for a comparison result, the (N+1) bit code yielding the N bit output signal. On detection of the (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for a most significant bit of the (N+1) bit code by replacing the (N+1) bit code by an alternative (N+1) bit code that yields the same N bit output signal, performing an additional comparison cycle using the alternative (N+1) bit code, determining, using comparison results of the additional comparison cycle and the preceding (N+1)cycle, a sign of a DAC capacitor mismatch error, and tuning programmable binary scaled calibration capacitors in parallel to a capacitor corresponding to the one of the most significant bits of the (N+1) bit code.

Circuit and method for DAC mismatch error detection and correction in an ADC

The present invention is related to an analog to digital converter circuit. The circuit comprises at least one input node for applying an analog input voltage signal (V), means for sampling said analog input voltage signal, a first array of capacitors arranged for receiving the sampled analog input voltage signal, a digital delay line connected to the first array of capacitors and arranged for being enabled by a clock generator and for generating a staircase or slope function by means of the first capacitor array, taking into account the sampled analog input voltage signal, a comparator arranged for comparing a converted signal with a reference voltage (V), said converted signal being a version of said sampled analog input voltage converted according to said staircase or slope function, and for generating a stop signal based on the comparison result thereby latching the digital delay line and thereby acquiring the digital code.

Asynchronous digital slope analog-to-digital converter and method thereof

An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to compare the analog input signal to a reference signal, a digital to analog converter operable to generate the reference signal corresponding to a state of a successive approximation register, and a control block connected to the comparator and to the digital to analog converter. The control block is operable to generate and receive a sequence of control signals according to a successive approximation algorithm, to perform a plurality of comparisons, and to update the state of the successive approximation register thereby generating the digital output.

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Eindhoven, Netherlands

Pieter Harpe