Semiconductor Components Industries, LLC

Piet Vanmeerbeek

Peter Moens

Abhishek Banerjee

Jaume Roig-Guitart

Marnix Tack

John Michael Parsey, Jr

Woochul Jeon

Ana Villamor

Filip Bogman

Ali Salih

Gary Horst Loechelt

Herbert De Vleeschouwer

Jaume Roig Guitart

Frederick Johan G Declercq

Pierre Gassot

Aarnout Wieers

An Enhancement Mode (e-mode) Metal Insulator Semiconductor (MIS) High Electron Mobility Transistor (HEMT), or EMISHEMT, with GaN channel regrowth under a gate area, is described. The EMISHEMT with GaN channel regrowth under a gate area provides a normally-off device with a suitably high and stable threshold voltage, while providing a low gate leakage current. A channel layer provides a 2DEG and associated low on-resistance, while a channel-material layer extends through an etched recess and into the channel layer, and disrupts the 2DEG locally to enable the normally-off operation.

Enhancement mode MISHEMT with GaN channel regrowth under a gate area

An opto-electronic High Electron Mobility Transistor (HEMT) may include a current channel including a two-dimensional electron gas (2DEG). The opto-electronic HEMT may further include a photoelectric bipolar transistor embedded within at least one of a source and a drain of the HEMT, the photoelectric bipolar transistor being in series with the current channel of the HEMT.

Opto-electronic HEMT

An electronic device can include a source terminal, a gate terminal, and a protection circuit. The protection circuit can include a gate section including a first electrode and a second electrode, wherein the first electrode of the gate section is coupled to the gate terminal; and a source section including a first electrode and a second electrode, wherein the first electrode of the source section is coupled to the source terminal. The protection switch can include a control electrode, a first current-carrying electrode coupled to the gate terminal, and a second current-carrying electrode coupled to the source terminal. The second electrode of the gate section, the second electrode of the source section, and the control electrode of the protection switch can be coupled to one another. In an embodiment, the electronic device can further include an electronic component that is protected by the protection circuit.

Electronic device including a protection circuit

An electronic device can include a drain electrode of a high electron mobility transistor overlying a channel layer; a source electrode overlying the channel layer, wherein a lowermost portion of the source electrode overlies at least a portion of the channel layer; and a gate electrode of the high electron mobility transistor overlying the channel layer; and a current limiting control structure that controls current passing between the drain and source electrodes. The current limiting control structure can be disposed between the source and gate electrodes, the current limiting control structure can be coupled to the source electrode and the first high electron mobility transistor, and the current limiting control structure has a threshold voltage. The current limiting control structure can be a Schottky-gated HEMT or a MISHEMT.

Electronic device including high electron mobility transistors

An electronic device can include a channel layer; an access region having an aluminum content substantially uniform or increasing with distance from the channel layer; and a gate dielectric layer overlying and contacting the channel layer. A process of forming an electronic device can include providing a substrate and a channel layer of a III-V semiconductor material over the substrate; forming a masking feature over the channel layer; and forming an access region over the channel layer. In an embodiment, the channel layer can include GaN, and the access region has an aluminum content that is substantially uniform or increases with distance from the channel layer. In another embodiment, the process can include removing at least a portion the masking feature and forming a gate dielectric layer over the channel layer. A dielectric film of the masking feature or the gate dielectric layer contacts the channel layer.

Process of forming an electronic device including an access region

A process of forming an electronic device can include forming a channel layer overlying a substrate and forming a barrier layer overlying the channel layer. In an embodiment, the process can further include forming a p-type semiconductor layer over the barrier layer, patterning the p-type semiconductor layer to define at least part of a gate electrode of a transistor structure, and forming an access region layer over the barrier layer. In another embodiment, the process can further include forming an etch-stop layer over the barrier layer, forming a sacrificial layer over the etch-stop layer, patterning the etch-stop and sacrificial layers to define a gate region, forming an access region layer over the barrier layer after patterning the etch-stop and sacrificial layers, and forming a p-type semiconductor layer within the gate region.

An electronic device can include a channel layer including AlGaN, where 0&#x2264;z&#x2264;0.1; a gate dielectric layer; and a gate electrode of a high electron mobility transistor (HEMT). The gate dielectric layer can be disposed between the channel layer and the gate electrode. The gate electrode includes a gate electrode film that contacts the gate dielectric layer, wherein the gate electrode film can include a material, wherein the material has a sum of an electron affinity and a bandgap energy of at least 6 eV. In some embodiments, the material can include a p-type semiconductor material. The particular material for the gate electrode film can be selected to achieve a desired threshold voltage for an enhancement-mode HEMT. In another embodiment, a portion of the barrier layer can be left intact under the gate structure. Such a configuration can improve carrier mobility and reduce Rdson.

Electronic device including a high electron mobility transistor including a gate electrode

An electronic device can include a transistor structure. In an embodiment, the transistor structure can include a channel region and a drift structure including different semiconductor base materials. In another embodiment, the transistor structure can include a source region and a drain structure including a first region, wherein the source region and the first region include different semiconductor base materials and have the same conductivity type. In another aspect, a process of forming an electronic device can include forming a semiconductor layer; forming a body region; patterning the body region and the semiconductor layer to define a trench having a sidewall; forming a first region of a drain structure along the sidewall of the trench, wherein the first region and body region include different semiconductor base materials and different conductivity types.

Electronic device including a transistor structure having different semiconductor base materials

An electronic device can include a transistor. The transistor can include a first layer including a first III-V material, a second layer overlying the first layer and including a second III-V material, and a third layer overlying the first layer and including a third III-V material. In an embodiment, each of the first and second layers includes Al, and the second layer has a higher Al content as compared to the first layer. In another embodiment, the transistor can further include a gate dielectric layer overlying the third layer, and a gate electrode of the transistor overlying the gate dielectric layer and the third layer. The transistor can be an enhancement-mode high electron mobility transistor. The configuration of layers can allow for a relatively higher threshold voltage, as compared to conventional enhancement-mode high electron mobility transistor, to be achieved without significantly affecting R.

Electronic device including a transistor including III-V materials and a process of forming the same

In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.

Semiconductor device having localized charge balance structure and method

An electronic device can include a vertical III-V transistor having a gate electrode and a channel region within a homostructure. The channel region can be disposed between a first portion and a second portion of the gate electrode. In an embodiment, the III-V transistor can be an enhancement-mode GaN transistor, and in a particular embodiment, the drain, source, and channel regions can include the same conductivity type.

Electronic devices including a III-V transistor having a homostructure and a process of forming the same

In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region.

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Sleidinge, Belgium

Piet Vanmeerbeek