Marvell International Limited

Marvellworld Trade Ltd.

Pierte Roo

Sehat Sutardja

Kenneth Thet Zin Oo

Wyant Chan

Jafar Savoj

Xiong Liu

Talip Ucar

William Lo

Francis Campana

Chih-Kai Kang

Olakanmi Oluwole

Shafiq M Jamal

Nick Chang

Tachien David Huang

A successive-approximation register (SAR) analog-to-digital converter (ADC) includes a SAR circuit configured to generate a digital code based on an analog input signal. A digital-to-analog converter (DAC) is configured to convert the digital code to an analog voltage. The SAR circuit is further configured to generate a digital output signal based on a comparison between the analog input signal and the analog voltage. A first capacitor is configured to provide a reference voltage to the DAC. An adaptive charging module is configured to stabilize the reference voltage provided to the DAC by selectively connecting to a supply voltage during a first operating phase of the ADC to store a charge in the adaptive charging module and selectively connecting to the first capacitor during a second operating phase of the ADC to combine the charge stored in the adaptive charging module with a charge of the first capacitor.

Adaptive charging systems and methods for a successive-approximation analog-to-digital converter

A voltage regulator includes a supply filter, a bias filter, and first and second circuits. The supply filter is configured to operate from a supply voltage, and to generate a filtered supply voltage at a first node. The supply filter includes a transistor and a capacitor. First and control terminals of the transistor receive the supply voltage. A second terminal of the transistor and a first terminal of the capacitor are connected to the first node. The first circuit is configured to operate from both the supply voltage and the filtered supply voltage, and to generate a second reference voltage based on an input reference voltage. The bias filter is configured to generate a filtered second reference voltage based on the second reference voltage. The second circuit is configured to operate from the filtered supply voltage, and to generate a regulated voltage based on the filtered second reference voltage.

Voltage regulator with positive and negative power supply spike rejection

A circuit including first and second reference ladders, a selection circuit, first and second analog to digital converters (ADCs), and a summer. The first reference ladder is configured to provide first reference voltages via first taps. The selection circuit is configured to select one of the first reference voltages. The second reference ladder is configured to, based on the selected one of the first reference voltages, provide second reference voltages via second taps. The first ADC is configured to convert the first version of the analog input signal to a first digital signal. The second ADC is configured to, based on the second reference voltages, convert the second version of the analog input signal to a second digital signal. The summer is configured to generate a digital output signal based on the first and second digital signals.

Method and apparatus for converting an analog signal to a digital signal based on reference voltages provided by reference ladders

In some implementations, a circuit includes an operational amplifier having a positive input, a negative input, and an output, the output being connected to the negative input; a first capacitor to receive the input signal; a second capacitor connected in series with the first capacitor, the second capacitor to provide a first signal to a positive input of the operational amplifier; a first resistor connected in series with the first capacitor, the first resistor to provide a second signal to the negative input of the operational amplifier; a second resistor to receive the input signal; a third resistor connected in series with the second resistor, the third resistor to provide a third signal to the positive input of the operational amplifier; and a third capacitor connected in series with the second resistor, the third capacitor to provide a fourth signal to the negative input of the operational amplifier.

Filter for attenuating undesired frequencies in a signal

A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.

Method and apparatus for controlling clocking of transceivers in a multi-port networking device

A system includes a transceiver configured to receive a composite signal. The composite signal is a composite of a transmit signal and a receive signal. A replica transmitter is configured to generate a replica transmit signal based on the transmit signal. A transmit canceller is configured to recover the receive signal at least in part by resistively summing the composite signal and the replica transmit signal.

Active resistive summer for a transformer hybrid

A voltage regulator includes a master circuit, first and second filters, and a slave circuit. The master circuit provides a second reference voltage based on a first reference voltage and a supply voltage. The first filter provides a filtered second reference voltage based on the second reference voltage. The second filter provides a filtered supply voltage based on the supply voltage. The slave circuit provides a third reference voltage based on the filtered second reference voltage and the filtered supply voltage. The second filter includes an NMOS transistor and a capacitor. The gate and the drain of the NMOS transistor receive the supply voltage. A first terminal of the capacitor is electrically coupled to a source of the NMOS transistor. A second terminal of the capacitor is electrically coupled to ground. The source of the NMOS transistor provides the filtered supply voltage.

Voltage regulators with large spike rejection

A level shift circuit includes a first latch circuit configured to receive a clock signal, a digital data signal, a first supply voltage, and a second supply voltage, and generate a first output signal based on the digital data signal. The first output signal has a first voltage level corresponding to the first supply voltage, and a second voltage level corresponding to the second supply voltage. At least one capacitor is configured to receive the first output signal, and retain a voltage value corresponding to the output signal. A second latch circuit is configured to receive the voltage value, a third supply voltage, and a fourth supply voltage, and generate a second output signal based on the voltage value. The second output signal has a third voltage level corresponding to the third supply voltage and a fourth voltage level corresponding to the fourth supply voltage.

Circuits and methods for level shifting a signal

First and second track and hold stages track and store an input voltage for a sample of an analog input signal. A coarse reference ladder provides a plurality of coarse references. The coarse reference ladder includes a first coarse reference and a second coarse reference ladder. A coarse ADC performs a first comparison of the input voltage and the coarse references and outputs a coarse output based on the first comparison. A switch matrix includes switches and is configured to close a switch corresponding to a coarse reference based on the coarse output. A fine reference ladder provides fine references. A fine ADC performs a second comparison of the input voltage and the fine references and outputs a fine output based on the second comparison. Logic outputs a digital output for the sample of the analog input signal based on the coarse output and the fine output.

Two-step subranging ADC architecture

A communication system including a phase-locked loop, a signal division controller, a divider, and a transmitter. The phase-locked loop is configured to generate an output signal in response to a common reference clock signal. The output signal is in phase lock with the common reference clock signal. The signal division controller is configured to receive a select signal, select an edge of a rising edge of the output signal and a falling edge of the output signal in response to the select signal, and generate a divider reset signal in response to the selected edge. The divider is configured to generate a communication clock signal by performing frequency division of the output signal. The divider reset signal controls a start time of the frequency division. The transmitter is configured to operate in response to the communication clock signal.

System and method for reducing electromagnetic interference and ground bounce in an information communication system by controlling phase of clock signals among a plurality of information communication devices

A line driver including a first driver circuit, a second driver circuit, and a first summing circuit. The first driver circuit generates a first component signal having a first polarity based on a first transmit signal, the bias signal, and the offset signal. The second driver circuit generates a second component signal having a second polarity based on a second transmit signal, the bias signal, and the offset signal. The first summing circuit sums the first and second component signals to generate a first differential signal. A first average current of the first differential signal for multiple symbols is greater than a second average current of a second differential signal for the symbols. The second differential signal is generated by summing a first biased signal and a second biased signal.

Class A-B line driver for gigabit Ethernet

In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.

A communication system including a plurality of communication devices configured to operate according to a plurality of communication clock signals, respectively, wherein the plurality of communication clock signals are based on a common reference clock signal. The communication system further includes a phase-locked loop configured to generate an output signal in response to the common reference clock signal, wherein the output signal is in phase lock with the common reference clock signal; a signal division controller configured to generate a divider reset signal in response to a binary select signal; and a divider configured to generate one of the plurality of communication clock signals by performing frequency division of the output signal, wherein the divider reset signal controls a start time of the frequency division.

In a high-precision signal detection apparatus and method for a high-speed receiver, signal detection occurs asynchronously of the incoming data. A comparison clock is generated by an oscillator whose effective capacitance is varied by a second, lower speed oscillator connected to the capacitance. This prevents the asynchronous sampling that occurs in a zero-crossing position in the incoming data from remaining in that position in subsequent sampling cycles, so that a valid signal is not missed by the detector.

Growing community of inventors

Sunnyvale, CA, United States of America

Pierte Roo