Alcatel Cit

Lignes Telegraphiques Et Telephoniques

Pierre Thepaut

Bernard Le Mouel

Pierre Jaffre

Jean-Francois Robin

A detector logic circuit restores the value 0 or .+-.1 of a ternary symbol converted into a signal on five levels 0, .+-.1 and .+-.2 as a result of class 1, type n=2 partial response transmission. Employing only binary logic circuits, it is connected to the output of a comparator which has four thresholds and which delivers a value representing the receive level by four binary signals. Two of these signals indicate positive overshooting of extreme and intermediate positive thresholds. The other two indicate negative overshooting of negative extreme and intermediate thresholds. The circuit delivers the values of the ternary symbols detected in the form of two binary components which are available at the output and stored for the duration of a symbol by two flip-flops. Both are generated by combinational logic devices of similar design utilizing OR and NOR gates.

Detector logic circuit for a sychronous transmission system for data

A synchronous digital cable transmission system comprises a transmitting terminal, intermediate regenerative repeaters and a receiving terminal. The transmitting terminal includes a data scrambler and a 6B/4T type binary-ternary line coder. The receiving terminal and the intermediate regenerated repeaters include a class 1 type n=2 partial response coding type receive signal shaping and filtering unit and a logic device for decrypting binary symbol superpositions resulting from the signal shaping and filtering processes. The receiving terminal also includes a 6B/4T binary-ternary decoder and a descrambler respectively compatible with the coder and the scrambler in the transmitting terminal.

Synchronous digital cable transmission system

Active filter cells comprising dipoles formed by means of capacitors and resistors having a pair of input terminals and a pair of output terminals, with, in each pair, a grounded first terminal and a non-grounded second terminal. They comprise two elementary networks each of which including: an operational amplifier having first and second inputs, the first of which is connected to a reference potential, and an output; a first dipole connected between said second input terminal of the cell and said second input of said amplifier; a second dipole connected between said second input and said output of said amplifier; and a third dipole connecting said output of said amplifier to said second output terminal of the cell. At least one of said networks contains a fourth dipole connected by one of its terminals to said second input of one of said amplifiers and by its other terminal to said second output terminal of the cell. The above-described arrangement can be combined with a third amplifier, of the differential type, whose output constitutes the output of the cell.

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Lannion, France

Pierre Thepaut