Hewlett-Packard Company

Hewlett-Packard Development Company, L.p.

Hewlett-Packard Development, L.p.

Pierre Sauvage

Robert H Hyerle

Marc Brandt

Pierre-Yves Thoulon

Brian Christopher Wyld

Eric Julien

Simon Morlat

Denis Pierrot

Pierre D Rondel

Jean-Michel Rosset

Configuration of a new point code connected to a SS7 network through a MTP level 3 aligned link, involves listening to point code status massages originating from distant point codes and forwarded on said link. When a message originating from an unknown distant point code is received, the table of distant point codes is updated with the point code number of the distant point code; at the same time, a primary route to the new distant point code through the link may be created. Therefore, configuration and testing of a new point code within an existing SS7 network, without having to re-enter the full network architecture, is facilitated.

Auto-configuration process for a point code in a common channel signaling network

The present invention relates to the field of tone detection and, more particularly, to the detection of dual tone multi-frequency (DTMF) tones in software based telecommunications systems. As modem telecommunications systems are becoming increasingly software based and typically require only a minimum of physical hardware, much of the necessary telecommunication functionality is now provided by software functions running on powerful computer servers. A common function which is required to be performed by telecommunications systems is that of dual tone multi-frequency (DTMF) detection. Accordingly, the present invention aims to provide an efficient software-based DTMF detection system that satisfies the ever increasing need for efficient software functions.

DTMF tone detection

The invention suggests providing in a processing system a licence controller (), for controlling use of a resource by processes (); for each process to be controlled, there is provided an inter-process communication () between the process and the licence controller. A process and the licence controller exchange through the inter-process communication of the process information regarding actual and allowed use of the resource by the process. According to this information, the process may be controlled, be it on a self-control basis or through control of the licence controller. Use of the resource to be dynamically adapted; high availability is guaranteed since processes may operate even when the licence controller fails.

Dynamic resource control in a processing system

A method of selectively sending a DTMF tone from a terminal to a first or a second destination, wherein the terminal sends a signal comprising at least one DTMF tone to an intermediate module prior to distribution to the intended destination, comprising: receiving the signal at the intermediate module; analyzing the nature of any DTMF tones in a portion of the received signal to determine the intended destination thereof; and sending a DTMF tone corresponding to the DTMF tones in the received signal to the determined destination.

DTMF control

High availability platform with fast recovery from failure by reducing non-response time-outs

A method is provided for automatically storing indications regarding conditions prevailing in a computer running a user application (1) that employs a library (2). This method involves providing an interface component (3) interposed between the user application and library. The interface component (3) is arranged to receive messages from the user application (1) destined for the library (2), pass on these messages to the library (2), and monitor and store indications regarding conditions prevailing in the computer at the time the messages are received or passed. Provision is made for dynamically changing the indications to be monitored.

Method of monitoring the operation of a computer

A fault tolerant platform is provided that comprises two systems running pairs of processes in the active and standby state, one process from each pair running on each system. Each system comprises a fault-tolerance controlling process, first communication channels provided between the fault-tolerance controlling process and the processes in the active or standby state running on its system, and second communication channels provided between the fault-tolerance controlling processes. Management of fault tolerance (that is, promoting a process in a standby state to the active state, and making a process in an active state exit from the active state) is handled by the fault-tolerance controlling processes. A generic management of fault tolerant processes is thus provided in which fault detection and switchover is carried out independently of the applications. The invention thus ensures efficient and coherent switchover between active and standby processes.

Generic fault tolerant platform

A Direct Memory Access (DMA) controller incorporates a memory test circuit that executes, using a dedicated system, repetitive memory read and write test phases such as are executed in conventional memory test methods by programs.

Circuit for testing microprocessor memories

The present invention relates to a testing method for an intermediate circuit between a microprocessor and surrounding circuits comprising a first set of access routes including lines of a data bus (D) and a control bus (C), and a second set of access paths comprising lines (AH) connected to other lines (CS) through a processing circuit (40). This method consists in providing in the intermediate circuit a test register (46) addressable by addresses ignored by the other elements of the circuit; writing test words in the test register through either one of the first and second set of as paths; reading the written words in the test register through the other set of access paths; and checking whether the read words correspond in a predetermined way to the test words.

Self testing computer system with circuits including test registers

The invention concerns a device for indicating the presence of optional components (01-04) that can be inserted on a microprocessor board, each component having a first pin (10) associated to a first contact (11) of the board connected to a first voltage corresponding to a predetermined logic state (0), the device comprising analyzing means (3) of each of the logic states present on specific lines respectively associated to the optional components. Each optional component has a specific pin (12) connected inside the component to said first pin (10) and associated to a second contact (14) of the board connected to the corresponding specific line.

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Notre Dame de Commiers, France

Pierre Sauvage