Microsemi Corporation

Integration Associates Incorporated

Carlingswitch, Inc.

Asic Advantage Inc.

Space Systems/loral, LLC

Spectrian Corporation

Quantic Industries, Inc.

Acs Communications

Avi Systems, Inc.

Pierre R Irissou

Etienne Colmet-Daage

Wayne Thomas Holcombe

Bernard Drexler

Michael A Fasano

Donald K Belcher

Sam Seiichiro Ochi

Brian Ben North

Joseph Stork Smith

William David Fahey

Dwight D Lynn

Jean-Luc Nauleau

David Truong

Thomas M Young

Kirk A Reid

Shu-Ren Chen

Hans R Camenzind

William H McCalpin

Theodore J Netoff

Stephen F Colaco

Pablito B Yra

Sergei Fedorjaczenko

Mark L Avory

Mathieu Sureau

David S Piazza

Russell Stevens

Stephane Legoff

David Parker

An over-current protection apparatus constituted of: a transistor disposed on a substrate; a first thermal sense device arranged to sense a temperature reflective of a junction temperature of the transistor; a second thermal sense device arranged to sense a temperature reflective of a temperature of a casing surrounding the substrate; and a control circuitry, arranged to alternately: responsive to the sensed temperature by the first thermal sense device and the sensed temperature of the second thermal sense device being indicative that the temperature difference between the transistor junction and the substrate casing is greater than a predetermined value, switch off the transistor; and responsive to the sensed temperature by the first thermal sense device and the sensed temperature by the second thermal sense device being indicative that the temperature difference between the transistor junction and the substrate casing is not greater than the predetermined value, switch on the transistor.

Over-current protection apparatus and method

Methods, systems, and devices are described for providing fault monitoring for light emitting diode (LED) circuits. Embodiments receive an indication from a fault control module that a fault has occurred in a portion of an LED module (e.g., a series string of LEDs). The fault may represent an open fault or a closed fault condition. In some embodiments, a monitoring module receives the fault indication and generates a further representation that the fault has occurred (e.g., for use by external components or systems). In other embodiments, the monitoring module in configured to further indicate which in the LED module has failed, and/or in what fault condition (e.g., open or closed).

Light emitting diode fault monitoring

Methods, systems, and devices are described for sensing a phase-cut dimming signal and outputting a control signal compatible with a switching power circuit. Embodiments of the invention generate at least one of a low-frequency pulse-wave-modulated control signal, an analog output control signal, or a digital (e.g., higher-frequency pulse-wave-modulated) output control signal. Some embodiments further provide preloading and/or startup control functionality to allow proper functioning of the circuitry under small-conduction-angle (i.e., highly dimmed) conditions.

Methods and apparatuses for phase-cut dimming at low conduction angles

A load current is limited to a safe level with a current protection logic circuit within a first selected interval after detection of a fault condition. The current protection logic circuit returns the load current to a normal level within a second selected interval after correction of the fault condition, wherein said safe level is less than one half of the normal level. The current protection logic circuit is a feature of a high side driver comprising at least two source drivers, each source driver being configured to switch an electrical load to a common power supply, and comprising a respective current protection logic circuit.

Source driver current fold-back protection

Methods, systems, and devices are provided for optimizing a bus voltage supplied to a switching power converter to keep the duty cycle of the switching power converter to within a desirable operating range. In some embodiments, the duty cycle of the switching signal used to drive the switching power converter is monitored (e.g., indirectly) to determine whether the duty cycle is approaching an undesirable level. For example, as the duty cycle decreases (e.g., approaches or crosses a certain threshold), embodiments decrease the bus voltage. This may, in turn, allow the switching power converter to output substantially the same output to the load, while using a more efficient (e.g., larger) duty cycle. Certain embodiments use similar techniques, along with certain bus voltage optimization techniques, to control a bus voltage as a function of feedback from multiple switching power converters.

Bus voltage optimizer for switched power converter

Methods, systems, and devices are described for providing output (e.g., current) sensing and feedback in high-voltage switching power converter topologies. Certain aspects of high voltage switching converter topologies may make output (e.g., current) sensing difficult. In some embodiments, a sampling module implements sample-and-hold techniques in a low-side switch converter topology to provide reliable current sensing. Embodiments of the sampling module provide certain functionality, including integration, blanking, buffering, and adjustable sampling frequency. Further, some embodiments include feedback functionality for generating a converter driver signal (for driving the switching converter) and/or a sample driver signal (for driving the sampling module) as a function of sensed output feedback from the sampling module.

Current sensing for high voltage buck converter

Phase-cut dimming circuit

A PIN photodiode and method for forming the PIN photodiode are shown where an intrinsic layer of the photodiode can be made arbitrarily thin and a second active region of the photodiode substantially shields a first active region of the photodiode. A fabrication substrate is lightly doped in order to form the intrinsic layer of the photodiode. A void is formed in a first surface of the fabrication substrate and a first active region of the photodiode having a first conductivity type is formed in the void. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication substrate is then lapped to a obtain a preselected thickness of the intrinsic layer. A depth of the void is selected such that a portion of the first active region is exposed at the second surface of the fabrication substrate after lapping. A second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate. The second active region may be formed such that it substantially surrounds the exposed portion of the first active region. A low resistance contact to the exposed portion of the first active region is formed, where the area of contact is small. Also, dummy differential contact can be formed on the topside of the photodiode adjacent to the low resistance contact for use with a differential input receiver circuit. Further, separate second active regions may be formed, with separate contacts and one of the regions covered by an opaque layer, to obtain a differential photodiode.

Shielded planar dielectrically isolated high speed pin photodiode and method for producing same

An integrated circuit power supply controller for use in a power supply that provides voltage regulating and current limiting functions. A current limit circuit is provided that includes a band-gap circuit for producing a reference voltage for precisely setting the current limit point, with the band-gap circuit being powered by a current sense voltage indicative of the load current rather than being powered by the regulated output voltage. Thus, the current limit circuit will operate even the power supply output is shorted. Voltage control circuitry is provided also includes a band-gap circuit for precisely controlling the magnitude of the regulated output voltage.

Controller for switch mode power supply

A method is shown for producing a distributed PN photodiode having a first active region of the photodiode that can be made arbitrarily thin. A fabrication substrate is doped to have a first conductivity type in order to form the first active region of the photodiode. A layer can also be formed upon the first surface of the fabrication substrate or a first surface of a handling wafer, where the layer can be an oxide layer, where a thickness of the oxide layer can be controlled to form a dielectric refractive reflector, a reflective layer, or a conductive layer. The first surface of the handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the first active region. A plurality of second active regions of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate. A contact having a plurality of connective traces is formed on the second surface of the fabrication substrate, where the connective traces are electrically coupled to the second active regions.

Method for producing a thin distributed photodiode structure

A method is shown for producing a PIN photodiode having low parasitic capacitance and wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A first glass layer is formed on a first surface of a handling substrate. The first surface of the handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication substrate is then lapped to a obtain a preselected thickness of the intrinsic layer. A second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate. A groove is etched from the second surface of the fabrication substrate through the intrinsic region to the first surface in order to isolate the photodiode. A second glass layer may be formed on a second surface of the handling substrate to further reduce parasitic capacitance.

Process for producing an isolated planar high speed pin photodiode with improved capacitance

A method is shown for producing a PIN photodiode using a reduced number of masks wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the intrinsic layer. A second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate. A groove is etched from the second surface of the fabrication substrate through the intrinsic region to the first surface in order to isolate the photodiode.

Process for producing an isolated planar high speed pin photodiode

A power supply arrangement including a transformer and a switching element coupled to a primary winding of the transformer and a power supply. The power supply includes a capacitor having a first terminal coupled to a junction of the primary winding and the switching element and a first diode coupled between the capacitor and an output node. The power supply further includes a discharge element, such as a resistor or a diode, coupled between the junction of the first diode and the capacitor and a power supply common. A voltage regulator, such as a Zener diode, is connected to the output node to produce a regulated voltage powered by the voltage applied to the transformer primary winding, with the regulated voltage being used to power the control circuitry.

Power converter having a low voltage regulator powered from a high voltage source

A method is shown for producing a PIN photodiode wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the intrinsic layer. And a second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate.

Planar dielectrically isolated high speed photodiode

Process for producing planar dielectrically isolated high speed pin

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Sunnyvale, CA, United States of America

Pierre R Irissou