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Telediffusion De France

Etat Francais (cnet)

Etabilissement Public Dit 'telediffusion De France'

Etat Francais, Administration Des P.t.t. (centre National D'etudes Des

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3g Licensing S.a.

Pierre Penard

Jean-Baptiste Dore

Marie-Hélène Hamon

Jean-Claude Carlach

Marie-Helene Hamon

Philippe Quenard

Jean-Pierre Vigarie

The invention relates to correcting codes for encoding and decoding a data signal. A signal including data variables is coded into a signal including the data variables and parity variables. The encoding and decoding operations are based on a parity check matrix comprised of a systematic matrix and a parity matrix and having rows corresponding coefficients of parity equations and distributed into decoding windows of same size. In order to increase convergence of the iterative decoding, the elements of at least one column of the systematic matrix associated with a decoding window are '0s', except for a single element which is a '1'. A data variable is only involved in one equation of the window and not involved in solving the equations of other windows as long as the solving of equations of the window is not achieved.

Encoding and decoding a data signal as a function of a correcting code

A method of low latency encoding of an input bit sequence (S) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E) applied to bits of the input bit sequence (S), using a first code; an interleaving step (E) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E) starts after a predetermined number &#x394; of bits have been interleaved, said predetermined number &#x394; of bits ranging between a first lower number &#x394;i of bits depending on one or more parameters of said interleaving step (E) and a first higher number &#x394;s of bits corresponding to the total number of bits to be processed during said interleaving step (E).

Fast encoding and decoding methods and related devices

A communication method and a communication system including a first entity () including an information source () and a coder device () connected by a channel () transmitting data to a second entity () including a decoder device (), the coder device () coding a data sequence sent by the information source () to form a set of code words from a parity check matrix including two matrix areas, each matrix area including a processing matrix, a connecting matrix including only one '1' per column and only one '1' per row, and a triangular matrix, and the decoder device () decoding a coded reception signal that is received by the second entity and is derived from the set of code words constructed in accordance with said parity check matrix.

Method and system for encoding a data sequence

The device and method disclosed relate to the field of electronic devices and methods enabling the transposition of any even-order square matrix, the elements of which are given in sequence. The goal is to provide for the transposition of sequences of data representing elementary image blocks, without any duplication of the memory space needed to store an elementary block, in optimizing the two parameters of operating speed and space occupied on silicon. This goal is achieved by a buffer memory divided into two identical storage half-planes, working together with a device for the sequencing of the reading/writing operations, providing simultaneously for a reading operation on one of the storage half-planes and a writing operation on the other half-plane.

Device and method with buffer memory, particularly for line/column

A random access memory (RAM) comprises memory cells each including an RS type flip-flop having complementary data inputs and transistors for forcing the flip-flop by that one of two data wires which is at a given level (high level for example) when a selection wire is at a first given level (high level for example). The flip-flop is connected to an output wire by circuitry for maintaining the output wire at the high level as long as the selection wire is at the first level and for causing the output wire to take the level corresponding to the condition of the flip-flop when the selection wire is brought to the other level. The transistors are preferably N-MOS for higher speed.

Growing community of inventors

Rennes, France

Pierre Penard