Texas Instruments Corporation

Pierre Michel Carbou

Pascal Guignon

Philippe Perney

Yves Leduc

Xavier Albinet

Jean-Christophe Jiguet

Paolo Giovanni Cusinato

Lorenzo Indiani

Paul Correia

Christian V Sorace

Frederic Boutaud

Jean-Louis Schevin

A power management bus for controlling power over multiple device subsystems includes a master power bus controller which transmits power management information to control one or more power resources through a transmit interface. The transmitted information is received at one or more receive interfaces. A broadcast message can be transmitted to control multiple power resources by subsystem, resource group and resource type. A single address message can be transmitted to control a single power resource. A power down can be initiated at any of the receive interfaces.

Distributed power management

The present disclosure describes systems and methods for driving light emitting diodes (LEDs). At least some embodiments include an LED driver system that includes a power supply, a plurality of current sources (each current source coupled between a common return resistor and one of a plurality of branches of series coupled LEDs, and each branch coupled between a corresponding current source and the power supply), and control logic coupled to the current sources (the control logic capable of controlling the current flow through each current source). Each of the current sources allows current to flow during one of a plurality of substantially non-overlapping time periods within a repeating time interval, each current source allowing current to flow during a different time period. The magnitude of the current flowing through each current source is substantially the same and is regulated based upon a feedback voltage across the common return resistor.

Unbalanced plural string LED driver with common return resistor

An amplifier comprising an analog amplifier which outputs a first current and a second current. The amplifier also comprises a first digital amplifier coupled to the analog amplifier, the first digital amplifier amplifies a modified version of the first current to produce a third current. The amplifier also comprises a second digital amplifier coupled to the analog amplifier, the second digital amplifier amplifies a modified version of the second current to produce a fourth current. The amplifier also includes connections configured to provide the first, second, third and fourth currents through a load.

Differential amplifier

An oscillator includes a resonator, such as a crystal ( ) coupled to first and second capacitor banks ( ). The first and second capacitor banks ( ) each comprise a plurality of capacitors ( ) coupled to the resonator ( ) through respective switching devices ( ) that may be selectively enabled. The switches ( ) are selectively enabled to couple a desired set of said capacitors ( ) to said resonator ( ). At least one of the switches ( ) is controlled with a clock signal having a programmable duty cycle from a sigma-delta modulator ( ) to enable at least one of said capacitors ( ) during a first phase of the clock signal and disable that capacitor ( ) during a second phase of the clock signal.

Numerically controlled variable oscillator

Current bit cell having a current source (P1), a transistor (P6) for detecting the presence of a digital signal bit (Bit) and a plurality of transistors (P2, P5, P7) for detecting at least one command signal (L, Lc) so as to command, on a first output (S1) of the cell, the appearance of a current delivered by the current source (P1) as a function of the digital signal (Bit) applied to the cell and of the at least one command signal (L, Lc), a transistor (P9) for detecting the presence of a bit (Bitz) complementary to the bit of the digital signal (Bit) and a plurality of transistors (P3, P4, P8) for detecting the complement (Lz, Lcz) of the at least one command signal (L, Lc), so as to command on a second output (S2) of the cell the appearance of a current delivered by the current source (P1) which is the complement of the current delivered on the first output (S1), the transistors for detecting the presence of bits and of the at least one command signal, the transistors for detecting the presence of complementary bits and of complementary command signals and the current source being embodied with the aid of field-effect transistors of the same type.

Current bit cell and switched current network formed of such cells

Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.

Controlled delay circuit

Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.

Controlled delay digital clock signal generator

An operational amplifier (10) is provided which includes a differential input stage (18) for receiving differential signals. A differential loop (30, 64), (86) amplifies said differential signals. The amplified differential signals are output on a pair differential output terminals (80, 84). A common mode loop (54), (30, 64) maintains the mean voltage of the amplified differential signals at a preselected value.

Performance operational amplifier and method of amplification

This digital-analog conversion system comprises a digital modulator (1) having several quantification levels formed by a second order Delta-Sigma modulator and a digital-analog converter and switched capacitors filter set (3) whose law of progression between the different analog levels is independent of the absolute and relative values of the constituent components of the said assembly.

Digital-analog conversion system including a digital modulator having

A sinusoidal signal generator having a frequency variable as a function of a selection signal applied to the generator. A clock generator (1, 2) is programmable as a function of the selection signal and adapted to provide a plurality of clock signals having variable frequencies. A D/A converter (7) generates from a difference fixed potential (V.sub.ss, V.sub.r), as a function of the clock signals utilized as sampling signals, a step signal having a sinusoidal envelope, of which the fundamental frequency is a function of the selection signal. A low pass filter (10) having transfer function which is dependent on the change in the fundamental frequency of the sinusoidal envelope (as controlled by the clock signals) rejects the harmonics contained in the step signal produced by the convertor (17), and provides a sinusoidal signal having a low harmnonic distortion.

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Tourrettes sur Loup, France

Pierre Michel Carbou