Chips and Technologies, Llc.

Pierre M Selwan

Morris E Jones, Jr

Arun Johary

Edward P Hutchins

Mahesh Siddappa

Minjhing Hsieh

Mel Walter Eatherington

David G Reed

A method and an apparatus for reading a given digital pulse signal of variable length in the domain of a first clock frequency and creating a pulse output signal that is synchronized in the domain of a second clock. The number of cycles the input pulse signal is active, in terms of the first clock, is the same number of cycles as the resulting output signal is active, where for the output signal the number of cycles is measured by the second clock.

Universal pulse synchronizer

In a video controller system including a video memory and first and second pluralities of functional circuits which access the video memory, requests for access to the video memory among more than one of the functional circuits are arbitrated by two levels of arbitration. In the first level of arbitration, a buffer in each of said first pluralities of functional circuits temporarily stores data read from or to be written to the video memory. A priority is assigned to requests for access from each of the functional circuits. A low limit and a high limit are assigned for each of the buffers. Requests for access to the video memory from all of the functional circuits are monitored. Each of the buffers is monitored to indicate whether the amount of data in each buffer is below the low limit or above the high limit. Access to the video memory is granted first to any requesting ones of the functional circuits whose buffers are below the low limit in order of the assigned priority. Access to the video memory is next granted to any requesting ones of the functional circuits whose buffers are not below the low limit and not above the high limit in order of the assigned priority. In the second level of arbitration, related functional circuits in the second plurality of functional circuits are grouped together under a selected functional circuit from said first plurality of functional circuits, and are provided data from the buffer in the selected functional circuit from the first plurality of functional circuits according to a priority determined by any of several methods known in the art.

Video memory controller with dynamic bus arbitration

A method and apparatus for improving bandwidth of sequential access to a display data memory. Display data and tag information related to consecutive data repetitions are stored. No display memory access is needed to output data to the CRT during the time periods when data is being repeated, thus increasing display memory bandwidth. Display data from a location in display memory is stored in a latch, and is output from the latch until the tag information indicates no more data repetitions occur.

Method and apparatus for performing run length tagging for increased

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Fremont, CA, United States of America

Pierre M Selwan