U.S. Philips Corporation

Telecommunications Radioelectriques Et Telephoniques T.r.t.

Pierre L Breant

Gilbert M Ferrieu

Alain C Fresnel

This circuit arrangement, which is connected to a delta modulation encoder operating with a sampling rate F and producing a first delta modulation signal, comprises means for producing the two bits b.sub.2n-1, b.sub.2n-2 which in this first signal precede each of the bits b.sub.2n occurring at the instants 2nT and having a rate F/2, a first flip-flop which is controlled at said instants 2nT for maintaining or not maintaining the state thereof, depending on whether the two above-mentioned bits b.sub.2n-1, and b.sub.2n-2 are identical or not, a second flip-flop to which the output signal of the first flip-flop is applied through a logic circuit, and which assumes either the state of the above-mentioned bit b.sub.2n or the state of the bit b.sub.2n-1, depending on whether the first flip-flop is in the one or in the other state. The output of this second flip-flop produces the desired delta modulation signal.

Circuit arrangement for halving the sampling rate of a delta modulation

By combining three single-phase output voltages of a synchro, signals are obtained which are proportional to the sine and the cosine of the angle of rotation of the synchro shaft. Said signals are sampled at predetermined instants by switching means controlled by a clock voltage, and are applied to computing means which form a signal representative of the speed of rotation of the shaft of the synchro and of a change in the altitude at which an aircraft flies.

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Clamart, France

Pierre L Breant