Alcatel Cit

Alcatel

Pierre Jaffre

Bernard Le Mouel

Jean-Francois Robin

Pierre Thepaut

Maurice Niquel

Christian Tanguy

A detector logic circuit restores the value 0 or .+-.1 of a ternary symbol converted into a signal on five levels 0, .+-.1 and .+-.2 as a result of class 1, type n=2 partial response transmission. Employing only binary logic circuits, it is connected to the output of a comparator which has four thresholds and which delivers a value representing the receive level by four binary signals. Two of these signals indicate positive overshooting of extreme and intermediate positive thresholds. The other two indicate negative overshooting of negative extreme and intermediate thresholds. The circuit delivers the values of the ternary symbols detected in the form of two binary components which are available at the output and stored for the duration of a symbol by two flip-flops. Both are generated by combinational logic devices of similar design utilizing OR and NOR gates.

Detector logic circuit for a sychronous transmission system for data

A synchronous digital cable transmission system comprises a transmitting terminal, intermediate regenerative repeaters and a receiving terminal. The transmitting terminal includes a data scrambler and a 6B/4T type binary-ternary line coder. The receiving terminal and the intermediate regenerated repeaters include a class 1 type n=2 partial response coding type receive signal shaping and filtering unit and a logic device for decrypting binary symbol superpositions resulting from the signal shaping and filtering processes. The receiving terminal also includes a 6B/4T binary-ternary decoder and a descrambler respectively compatible with the coder and the scrambler in the transmitting terminal.

Synchronous digital cable transmission system

First and second parallel-connected calculating units (12, 18) simultaneously calculate the sum .SIGMA..sub.n =.SIGMA..sub.n-1 +Sn and the difference .SIGMA.'.sub.n =.SIGMA..sub.n-1 -Sn where the Sn is equal to one-half of the difference between the number of 1-bits and the number of 0-bits in a binary word to be transmitted and: ##EQU1## A comparator circuit (22) compares the signs of .SIGMA..sub.n-1 and Sn and the result of the comparison is used to reset the output from one of said calculating units to zero. The sum unit (12, 18) is reset to zero when the signs are different and the difference unit (13, 19) when the signs are equal, in which case the bits of the transmitted word are inverted. The sign comparison bit is also transmitted as an additional bit of the transmitted word.

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Lannion, France

Pierre Jaffre