Advanced Micro Devices Corporation

Pierre F Haubursin

Ching Yu

Din-I Tsai

Robert Alan Williams

David Balmforth

A mechanism that captures and reports interrupt events occurred in various portions of a network interface controller. As different clocks control these interface controller portions, the interrupt request signals corresponding to the interrupt events are created in different clock domains. The first stage of the mechanism for capturing and reporting interrupt events detects interrupt events having different duration, and produces an interrupt synchronizing signal asserted during at least one period of a local clock signal. The second stage serves as a positive edge detector to produce an interrupt positive edge detect signal asserted during three clock periods. The third stage supports a read operation performed by a host signal corresponding to the detected interrupt event to read an interrupt request. Finally, the fourth stage of the mechanism for capturing and reporting interrupt events acts as an interrupt register to store an interrupt signal corresponding to the detected interrupt event and to produce an interrupt request signal sent to the host.

Mechanism for capturing and reporting interrupt events of different clock domains

An output driver that may be configured to operate as a totem-pole driver, or as an open-drain driver. The output driver comprises a totem-pole driver coupled to an output pin. A control circuit is coupled to the output enable input of the totem-pole driver. The control circuit is supplied with an open-drain control signal controlled by the user interface. When the open-drain control signal is at a first logic level, the output driver operates as an open-drain driver. When the open-drain control signal is at a second logic level, the output driver is configured to operate as a totem-pole driver.

Method and system for switching between a totem-pole drive mode and an open-drain drive mode

A system for tracing read and write accesses to selected registers is provided in a network interface. The system has a read trace register containing a separate bit for each register to be monitored for read access by an external CPU. A write trace register is provided with a bit for each register to be monitored for write access by the CPU. When the CPU performs read or write access to a monitored register, a decoder that decodes an address signal from the CPU produces a trace select signal supplied to the read trace register and/or write trace register. In response to the trace select signal, the bit representing the monitored register is set to a predetermined logic state indicating that the monitored register was accessed by the CPU for reading and/or writing.

Software read and write tracing using hardware elements

An apparatus and method ensure that only one data processor, within a multiprocessor system, performs operations associated with an interrupt register having information corresponding to a particular interrupt. An interrupt register from a plurality of interrupt registers is selected via an address decoder, and data bits from the selected interrupt register are steered to a data bus. Each interrupt register has a corresponding trailing edge detector which clears the data content of the interrupt register after a first one of a plurality of data processors has read the data bits of that interrupt register on the data bus to service that particular interrupt. In this manner, a second one of the data processors which also attempts to service that particular interrupt reads the cleared content of that interrupt register. Upon reading the cleared content of that interrupt register, the second one of the data processors is alerted to return to a foreground task since that particular interrupt has already been serviced. The present invention also provides an option for not clearing an interrupt register. In addition, the present invention may include a mechanism for processing interrupt information data bit portions at a time by data type within an interrupt register.

Mechanism for synchronizing service of interrupts by a plurality of data

An m bit counter which counts to a desired clock frequency F.sub.D given a central clock frequency F.sub.C is emulated by a chain of two subcounters. The ratio r of the central clock frequency F.sub.C over the desired clock frequency F.sub.D is factored to r=F.sub.C /F.sub.D =2.sup.n * p, where n is one of zero or an integer (i.e., 0, 1, 2, 3 . . . ) and where p is an integer. A 1 to p subcounter counts from 1 to p driven by the central clock frequency F.sub.C. The output of the 1 to p counter is an intermediate clock frequency which includes a pulse every periodic count from 1 to p. The intermediate clock frequency drives a m+n bit subcounter with the n bits being appended as the least significant bits of the m+n bit subcounter. In this manner, the m most significant bits of the m+n bit subcounter count to the desired clock frequency F.sub.D.

Emulation of an m bit counter driven by a desired clock frequency given

Circuit and method is disclosed which prevents contention on a pulse-code modulated (PCM) bus, when different drivers are transmitting during adjacent time slots. The driver circuit switches automatically from a strong driver to a weak driver depending on whether a signal level is merely repeating or whether the level is transiting. Also the driver always employs the strong driver at the onset of transmission.

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Sunnyvale, CA, United States of America

Pierre F Haubursin