France Telecom

Etat Francais Represente Par Le Ministre Delegue Des Postes Et

Other

Telediffusion De France

Etat Francais Represente Par Le Ministere Des Postes, Des

Etat Francais (cnet)

Etat Francais, Represente Par Le Ministres Delegue Des Postes Et

Pierre Duhamel

Hedi Hmida

Yannick Mahieux

Pascal Scalart

Abdellatif Benjelloun Touimi

Jean-Claude Carlac'h

Adil Mouhssine

Abdelkrim Benamar

Zhijian Mou

Christine Guillemot

Hendrik Hollmann

Michel Cand

The invention relates to a method for quantifying components, wherein certain components are each determined based on a plurality of audio signals and can be calculated by the application of a linear conversion on the audio signals, said method comprising: determining a quantification function to be applied to the components by testing a condition relative to an audio signal and depending on a comparison made between a psycho-acoustic masking threshold relative to the audio signal and a value determined based on the reverse linear conversion and quantification errors of the components by the function.

Quantization after linear transformation combining the audio signals of a sound scene, and related coder

To estimate the response of a system to an input signal, on the one hand the input signal and on the other hand an observation signal, a component of which is said response to the input signal, are received, an error signal is determined by subtracting from the observation signal the input signal filtered by an identification filter representative of the response of said system, and the coefficients of the identification filter are adapted by taking into account the input signal and the error signal. If the adaptation takes into account an adaption stepsize .mu..sub.t, the latter is varied according to: .mu..sub.t =a/(c+d. P2.sub.t /P1.sub.t), where a, c and d denote positive constants, P1.sub.t denotes an estimate of the power of the input signal and P2.sub.t denotes an estimate of the power of the observation signal or of a disturbance component of said observation signal. The variable .mu..sub.t can also be employed to adapt the gains of an echo canceller with adaptive gains.

Process and device for adaptive identification and adaptive echo

After a windowing operation h(n) performed by space-time weighting of the samples, a method and an apparatus for encoding-decoding a digital signal comprising a sequence of samples x(n) consists in performing a modified discrete cosine transform of the samples to calculate the even order transformation coefficients: ##EQU1## for k .epsilon.[0, . . . , N/2-1] with YN-k=-Yk-1 The coefficient Y2k are expressed in the form of an invertible complex transformation: ##EQU2## for k=0, . . . , N/4-1 with y'n=x2n.h2n y'n xN-2n-1.hN-2N-1 W4N=cos(2.pi./4N)+j.sin(2.pi./4N) The invertible comples transformation is calculated using an auxiliary calculation equation: ##EQU3## with: zn=(y2n-yN/2-1-2n)+j(yN-1-2n+yN/2+2n) The invention is applicable to encoding and decoding digital audio or video signals.

Method and apparatus for encoding-decoding a digital signal

A binary multiplier circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced. A fixed operand is multiplied by a variable operand by storing a partial result of the multiplication using an accumulator and a shift register with the binary calculation circuit. A two-input multiplexer has one of its inputs connected to the output from the register and an output connected to the input of the register. The variable operand is applied serially to a control input of the multiplexer.

Binary multiplier circuit with improved inputs

Process and device for the compression of image data by a mathematical transformation implemented at low cost, particularly for the transmission at reduced speed of sequences of images. The objective is to provide an economical method in 'silicon area - processing speed' cost to implement a mathematical transformation of the DCT type, on arrays of pixels, suitable for image compression. According to the invention, the method consists essentially of combining a permutation (1) of each block of pixels with a series of one dimensional FFT (211, 213). A series of variants is obtained by adding or not adding steps of matrix calculation (22) of reconstitution of a complex 2D-FET, of rotations (3) of reconstitution of the DCT, and/or of suppression of the imaginary coefficients.

Process and device for the compression of image data by mathematical

A binary calculation circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced.

Binary adder circuit with improved inputs

The multiplier according to the invention comprises N shift registers (RD.sub.O, . . . , RD.sub.N-1) containing the words x.sub.i on B bits, N conditional adders (AdC.sub.O, . . . , AdC.sub.N-1) each adding to the partial sum which they receive a constant coefficient (a.sub.1), conditional on the value of the bit (x.sub.i,j) which they receive from the associated register (RD.sub.1) and an adder accumulator (AdAc). The digital filter using such a multiplier also comprises a parallel word input register.

Generalized digital multiplier and digital filter using said multiplier

A circuit for performing binary calculation, the circuit being of the type having at least one cell possessing: a first bit input (Ai), a second bit input (Bi), a carry-in input (Ri-1), circuitry (1600) for generating a two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi), circuitry (1800) for producing a result signal, and circuitry (1900) for producing a carry-out signal (Ri), the circuitry being constituted by multiplexed logic. The complemented two input bit exclusive-OR signal (Ai.sym.Bi) is produced by inverting the two input bit exclusive-OR signal (Ai.sym.Bi), thereby making it possible to utilize only 15 transistors in the most cut-down version of the circuit. The invention also relates to a circuit (20) having an addition cell (22) calculating the sum of the input bits and a subtraction cell (24) calculating the difference of the input bits. The circuitry (1600) for producing the two input bit exclusive-OR signal (Ai.sym.Bi) and its complement (Ai.sym.Bi) are then used in common both by the addition cell (22) and by the subtraction cell (24).

Binary calculation circuit

A multipler having two inputs and one output. Each input receives a binary input signal through a block which performs an arithmetic base change and encoding and a NTT circuit. The NTT is performed with a modulus M of the form 2.sup.P -2.sup.q +1. The output is applied to a block for decoding and return to the original arithmetic base in series relation with a NTT.sup.-1 circuit.

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Pierre Duhamel