International Business Machines Corporation

Pierre Debord

Alain R Blanc

Rene J Glaise

Bernard Brezzo

Claude Gomez

Alain Saurel

Jean-Louis H Marijon

Albert X Widmer

Patrick J Jeanniot

Pierre L Beaudouin

A backplane system allowing a very large number of interconnections between high-connectivity printed circuit boards and a backplane is disclosed. The backplane is fragmented into a plurality of backplane parts that comprise connectors on their edges to mate connectors arranged on the high-connectivity printed circuit boards. These backplane parts may also include other connectors on their edges to couple to extension printed circuit boards requiring less interconnections or cables. Interposers can be used to link several backplane parts and provide enhanced air circulation.

Fragmented backplane system for I/O applications

A flow control process for a switching system having at least one switch core connected through serial communication links to remote and distributed Protocol Adapters or Protocol Engines through Switch Core Access Layer (SCAL) elements. For each input port i, the SCAL element contains a receive Protocol Interface corresponding to the adapter assigned to the input port i and a first serializer for providing attachment to the switch core by means of a first serial communication link. When the cells are received in the switch core, they are deserialized by means of a first deserializer. At each output port, the cells are serialized again by means of a second serializer and then transmitted via a second serial communication link, to the appropriate SCAL. The SCAL contains a second deserializer and a transmit Protocol Interface circuit for permitting attachment of the Protocol Adapter. The flow control process permits two flow control signals, a flow control receive (FCR) from the core to the SCAL, and a flow control transmit (FCX) from the SCAL back to the core. For transmission of the FCR signal in response to the detection of local saturation in the switch core, the process causes transfer of an internal FCR signal to the serializer located within the saturated core. The FCR is introduced in the normal data flow to be conveyed through the second serial link to the remote SCAL corresponding to the saturated input port of the core. An internal control signal can be transmitted to the Protocol Interface that is originating too many cells which results in the overloaded input port of the core. For the transmission of the FCX signal in response to the detection of a saturated Protocol Interface element at one output port, the process generates an internal control signal to the serializer located in the SCAL element. The serializer can introduce a FCX signal in the normal data flow which is conveyed to the core and then decoded by the deserializer in the core. Thus, the core can be informed of the saturation condition that has occurred in the considered output port. Particular adaptations are provided in which the switching system is arranged in a set of individual switching structures mounted in a port expansion mode.

Flow control process for a switching system and system for performing the same

A flow control process for a switching architecture having a central switch core with associated distributed Switch Core Access Layers communicating with the core by means of serial data communication links. The serial links carry data flows that are coded in accordance with the 8B/10B coding, where two among the three comma characters are used for creating an additional specialized flow control channel. When the cells are idle or empty, the nature of the comma character that appears at the beginning of the cell provides the appropriate flow control bit information. For instance, should the K.28.5 character be detected, the receiving entity (either the switching structure or a distributed SCAL element) decodes the character as positive flow control information, corresponding to a request to reduce the incoming data flow. Also, should the K.28.1 character be decoded, then the receiving entity decodes this as information according to which no reduction in the data flow is requested. When the incoming flow provides data cells, the invention uses a predetermined bit within the data cell, generally that immediately following the beginning of the cell, in order to carry the flow control information.

Flow control process for a switching architecture using an out-of-band flow control channel and apparatus for performing the same

A method and apparatus for managing contention in a self-routing switching architecture based on a set of n&times;n individual switching structures that are connected in a port expansion mode by means of fan-out and fan-in circuits providing access of the Switch Core Access Layer (SCAL) to the different input and output ports of the switching core. The fan-in circuits use an arbitration mechanism for providing a token to the switch that is allowed to deliver the next cell and the arbiter operates from a detection of a special comma character in accordance with the 8B/10B coding scheme which is introduced in the data flow between the individual switching structures and the fan-in circuits. This provides a compensation for the difference in transfer delays of the cells even when high switching speed and long length of the physical media are involved.

Method and apparatus for managing contention in a self-routing switching architecture in a port expansion mode

An apparatus and method for correcting data words from a memory is provided in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure and a single soft error located in a different package. The invention involves the use of an error correcting code which gives a first syndrome when the data word has suffered a first error coming from at least one error in a first package and a single error in a different second package, which also gives a second syndrome when the data word has suffered a second error coming from at least one error in the above first package, and a single error in a third package. The error correcting code is such that equality of the first and second syndromes results in the equality of the first and second errors.

Extended errors correcting device having single package error correcting

Disclosed is a dynamic compensation circuit for correcting the residual offset voltage encountered in an analog-to-digital conversion chain. Samples of an analog signal having an average value equal to 0 are provided to a first input of a comparator, the second input of which receives a reference signal generated through a D to A converter under control of a control logic circuit. A sample and hold circuit with the comparator causes a DC offset of the output signal level which is to be dynamically corrected by the compensating circuit of the invention. The DC offset causes the duty cycle to differ from one by an amount .DELTA.DC which will be the error curve signal of the compensation circuit. The compensating circuit reduces the .DELTA.DC to 0 by adding to the signal a DC voltage opposite to and of equal magnitude to the offset voltage level.

Dynamic zero offset compensating circuit for A/D converter

A noise reduction scheme for a photosensitive self scan system includes an array of photosensitive elements producing video signals and first and second pluralities of switching elements, one element of each of the pluralities of switching elements being connected to one photosensitive element of the array. A first video line connects each element of the first plurality of switching elements to a first input terminal of a summing device such as a differential amplifier and a second video line connects each element of the second plurality of switching elements to a second input terminal of the differential amplifier. Shift register means operated by clock pulses is provided to control the operation of each of the elements of the first plurality of switching elements to sequentially couple the photosensitive elements to the first input terminal and to apply periodically only clock pulse noise signals through the gate drain capacitance of the second plurality of switching elements to the second input terminal of the differential amplifier, so as to produce at the output of the amplifier a video signal substantially free of noise signals created by the clock pulses.

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Tourrettes sur Loup, France

Pierre Debord