Micron Technology Incorporated

Micron Semiconductor, Inc.

Innovative Silicon S.a.

Ovonyx Memory Technology, LLC

Round Rock Research, LLC

Innovative Silicon Isi Sa

Pierre C Fazan

Gurtej S Sandhu

Viju K Mathews

Yauh-Ching Liu

Hiang C Chan

Charles H Dennison

Howard E Rhodes

Nanseng Jeng

Shubneesh Batra

Ruojia R Lee

Thomas Arthur Figura

Paul J Schuele

Brent Keeth

Tyler A Lowrey

Kirk D Prall

Aftab A Ahmad

Werner Juengling

Klaus Florian Schuegraf

Pai-Hung Pan

Li Li

Zhiqiang (Jeff) Wu

Martin Ceredig Roberts

Fernando N Gonzalez

Kunal R Parekh

Thomas M Graettinger

Bohr-Winn Shih

Trung Tri Doan

John K Zahurak

Gordon A Haller

Michael Allen Van Buskirk

D Mark Durcan

Serguei Okhonin

Kelly T Hurley

Viktor Koldiaev

Randal W Chance

Christian Caillat

Jungtae Kwon

Steven D Cummings

Guy T Blalock

Randhir P Thakur

Donald L Westmoreland

Phillip G Wald

Ardavan Niroomand

Joseph J Karniewicz

David L Dickerson

Akram Ditali

Mohammed Anjum

Chuck H Dennison

Roy L Maddox, Iii

Roy Maddox

An integrated circuit device having (i) a memory cell array which includes a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells have a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions.

Integrated circuit having memory cell array including barriers, and method of manufacturing same

Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.

Manufacturing process for zero-capacitor random access memory circuits

Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation, a second region connected to a bit line extending a second orientation, and a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Techniques for providing a semiconductor memory device

A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

Semiconductor memory device

An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells include a layout that provides a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions. A plurality of electrical contacts, wherein an electrical contact is disposed on a (i) common first region and/or second region and (ii) barrier(s) associated therewith which is disposed therein and/or therebetween. Also disclosed are inventive methods of manufacturing such integrated circuit devices.

Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-) islands and form elongated vias, in a succession of processing steps to build dense memory arrays.

Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells.

High density integrated circuitry for semiconductor memory having memory cells with a minimum capable photolithographic feature dimension

A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

Method of forming a thin film transistor

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, integrated circuit device includes memory portion having, for example, PD or FD SOI memory cells, and logic portion having, for example, high performance transistors, such as Fin-FET, multiple gate transistors, and/or non-high performance transistors (such as single gate transistors that do not possess the performance characteristics of the high performance transistors). In another aspect, the present invention is directed to a method of manufacture of such integrated circuit device.

Integrated circuit device, and method of fabricating same

Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells, more preferably, at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.

Integrated circuitry for semiconductor memory

Thin film transistors and semiconductor constructions

A storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode including a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. An insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant.

Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same

An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.

Method for forming a storage cell capacitor compatible with high dielectric constant materials

Growing community of inventors

Boise, ID, United States of America

Pierre C Fazan