France Telecom

Etat Francais Represente Par Le Ministre Des Postes, Telecommunications

French State Represented by Minister of the Post, Telecommunications &

Servel, Michel

Rouaud, Yvon

Boyer, Pierre

Pierre Boyer

Michel Servel

Jean-Pierre Coudreuse

Jean-Paul Quinquis

Fabrice Guillemin

Olivier Dugeon

Christophe Mangin

Alain Girard

Didier Tranchier

Jacqueline Boyer

Bit rate reservation is effected with the aid of a reservation cell containing a requested bit rate transmitted from a calling terminal to a called terminal via switching nodes of an asynchronous network. At each node, a bit rate increase request is at least partially satisfied even if the difference between the requested bit rate and the current bit rate is greater than the bit rate available at the node. The node replaces the requested bit rate in the reservation cell by a new bit rate lower than the latter so that the called terminal receives the lower new adopted bit rate by the nodes. An acknowledgement cell retransmitted with this lower new bit rate by the called terminal renders uniform the adopted bit rate at all the nodes. If no acknowledgement cell has been received after a predetermined time-delay the nodes revert to their initial state, with the current bit rate preceding the bit rate reservation.

Bit rate reservation at switching nodes of an asynchronous network

A process is described for spacing over time the transmissions of cells that belong to messages. The value of the address of the first cell of the message is stored in relation to the clock-time of the sending. At each time given by a local clock-time, the address value is read in relation to said local time. The cell having said address is sent. Then, the sending clock-time of the next cell of said message is computed. The address of the next cell of the message is determined. The address value of the next cell is stored in relation to the clock-time of its computed transmission. The invention also relates to spacing devices which are used to execute this process.

Procedure for time spacing of transmittals from cells relating to

A queueing circuit serves an asynchronous switching circuit. A number of input circuits are connected to inputs of a switching network in a one-to-one relationship with the outputs of the switching matrix. During its own time slot, each of the input circuit has a series of availability signals which are assigned to time slots that are later than the input circuit's own time slot. These availability signals indicate the availability condition at the matrix output for enabling an emission of a data cell during the time slot identified by the availability signal. Based upon the availability signal, the cell is released from a memory storage during an available one of the later time slots.

Input waiting line system especially provided for connection to the

A data transmission system has a time interval allocation system with a time interval management unit (UGIT) and a plurality of counters (CSO.sub.1 to CSO.sub.n) connected to one another in a cascaded series. The input of a counter (CSO.sub.i) is connected to the output of the preceding counter (CSO.sub.i-1) in the series. The input of the first counter (CSO.sub.1) is connected to the output of the time intervals management unit. Each counter (CSO.sub.i) is associated with an input carrying a time interval allocation demand signal (dem.sub.i) and provided with a command input for receiving the allocation demand signal (dem.sub.i) and delivering either the time interval value (ITin) present on its input if the allocation demand signal (dem.sub.i) is inactive, or the time interval value present on its input increased by a unit (ITin+1) if the demand signal (dem.sub.i) is active. The output of each counter (CSO.sub.i) is connected to the input of a register (RegAd.sub.i), having a command input for receiving the corresponding demand signal (dem.sub.i). Then, each register (RegAd.sub.i ) delivers an allocated time signal (ITa) if the corresponding demand signal (dem.sub.i) is active.

Allocation of time interval systems and multiplexers provided with one

A device for initiating multiple timings has a supply of clock pulses. At each clock pulse, an entering cell is stored in a communication system with asynchronous time switching. The stored cell belongs to a virtual communication circuit that carries a number in the label of the cell. A random access, read-write timing memory (MT) has a plurality of addressable zones which normally store null or inactive bits. The memory (MT) is alternately addressed for writing and for reading. The memory (MT) comprises a data input (ED) to store, in a zone addressed for writing, a parameter bound to a characteristic of a virtual circuit. A data output (SD) delivers the content of the memory zone addressed during reading.

Device for the initiation of multiplex timings in an asynchronous

There is assigned to each virtual circuit a period (pm) corresponding to the theoretical minimum period between two consecutive cells of the virtual circuit and a maximum time limit (dm). The imaginary time of emission on the output multiplex of the last cell belonging to each virtual circuit is stored, and, upon the arrival of a new cell of a virtual circuit, a threshold time calculated by adding its actual time of arrival and the maximum time limit is compared with the imaginary time of emission expected of the new call in the course of being processed, the time being calculated by adding the imaginary time of emission of the last cell emitted and the minimum period (pm). If the result of this comparison shows that the threshold time is earlier than the imaginary time of emission expected (tde+pm), the incoming cell is not re-emitted, whilst, if it shows that the threshold time is later than the imaginary time of emission expected (tde+pm), it is emitted on the output multiplex, the imaginary time of emission of the incoming cell then being calculated, then stored in relation to the virtual circuit to which the incoming cell belongs.

Method for controlling the delivery from cells

The method embodying the invention authorizes communication bit rate reservations in a packet switching network. According to the method, a new communication is only accepted by the network if the communication does not exceed a maximum bit rate flowable by the switches of the network. A packet switch in the network comprises a bit rate reservation device for memorizing bit rate informations that are representative of total bit rates flowed by the switch and for processing said information as a function of data carried by service packets. The bit rate reservation device mainly comprises registers respectively associated with multiplex ways of the switch for memorizing the bit rate informations, an adder for incrementing and decrementing the bit rate informations as a function of service packet data, and a comparator for detecting overstepping of the maximum flowable bit rate.

Bit rate reservation in an asynchronous packet network

A device embodying the invention for a packet time-division switcher comprises essentially a circuit for detecting beginnings and ends of load interruption periods in the switcher, and a period counter. The detecting circuit is connected to a plurality of input buffer quenes of the switcher and detects a load interruption when all queues signal a state of packet emptiness. A time base of the switcher is inhibited at the end of a period of predetermined duration established by the counter and following the detection of a load interruption. Said duration is predetermined so as to complete the switching of a packet that has been begun. Once the time base is inhibited, the operating of the switcher is interrupted and its power consumption becomes very low. The time base is freed as soon as a packet is received by the queues, and the switcher resumes operating.

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Lannion, France

Pierre Boyer