Bull Sas

Pierre Axel Lagadec

Dominique Rigal

Laurent Marliac

Vivian Blanchard

Saïd Derradji

Disclosed is a method for test traffic generation, at test-sending switches for a network of calculation nodes, and of inspection of this test traffic, at test-receiving switches of this network, including: the generation and sending of test traffic, at least at a selected test-sending input or output port of one selected test-sending switch, sent to at least one selected test-receiving input or output port of a selected test-receiving switch, where the test traffic is generated and sent by a traffic generation component configured as an additional input of the selected test-sending input or output port, where the test traffic is inspected by a traffic inspection component configured for filtering the output of the selected test-receiving input or output port.

Method for test traffic generation and inspection, and associated switch input or output port and switch

A method for sending data, from an upstream device to a downstream device, including sending a piece of data from one among a plurality of virtual channels sharing the same input buffer memory of the downstream device, if this virtual channel uses a number of memory locations of the input buffer memory strictly less than a current ceiling. It further comprises measuring a communication latency between the upstream and downstream devices, and calculating the current ceiling from the measured latency.

Method for sending by an upstream device to a downstream device data from a virtual channel sharing a same input buffer memory of the downstream device, corresponding computer program and system

Growing community of inventors

Villeneuve Loubet, France

Pierre Axel Lagadec