Semiconductor Components Industries, LLC

Alcatel

Alcatel Mobile Communication France

Alcatel N.v.

Pierre Andre Genest

Fuji Yang

Joel Turchi

Frank Op 't Eynde

Hassan Chaoui

Michael Bairanzade

Arnaud Parisel

Jan Jezik

Arnaud Maecker

Corinne Berland

Nicolas Moeneclaey

Damien Luc Fran&ccedil;ois Macq

Eric Dussauby

Cross-coupled charge-pumps. At least some of the example embodiment are methods including: pumping charge from a first capacitor through a first field effect transistor (FET) to a voltage output and from a second capacitor through a second FET to the voltage output of the charge pump; refreshing charge to a third capacitor and a fourth capacitor during the pumping of charge; electrically isolating the first through fourth capacitors during a dead time; and then pumping charge from the third capacitor through a third FET to the voltage output and from the fourth capacitor through a fourth FET to the voltage output of the charge pump; and refreshing charge to the first capacitor and the second capacitor during the pumping of charge from the third and fourth capacitors.

Cross-coupled charge-pumps

Active post-power loss discharging of capacitors is provided. In an integrated circuit having a startup behavior depending on a capacitor voltage, a discharge transistor is provided to discharge the capacitor. A power-down discharger actively drives the discharge transistor after a power supply voltage drops below a threshold. The power-down discharger may include, or be coupled to, an internal capacitance that is charged when the power supply voltage is above the threshold, thereby storing sufficient energy for later driving of the discharge transistor. A diode is employed to ensure that the loss of power does not drain away the needed energy until after the discharge has been completed. One illustrative discharging method includes: sensing a condition indicative of power supply voltage loss for an integrated circuit; and actively driving the discharge transistor into a conducting state. The sensing may include driving the discharge transistor inversely to a signal from a pin.

Power-down discharger

In an embodiment, a gate driver circuit and/or method therefor may include configuring the gate driver circuit form a drive current to supply to a gate of an MOS transistor wherein the value of the drive current is a minimum value that can be supplied to the gate without increasing a charge stored on a gate-to-source capacitance of the MOS transistor; configuring the gate driver circuit to change the value of the drive current responsively to changes of a Vgs of the MOS transistor.

Adaptive MOS transistor gate driver and method therefor

In one embodiment, a charge-pump controller is formed to control a value of current supplied to a load.

Charge-pump controller

In one embodiment, a charge-pump controller is formed to control a value of current supplied to a load. One embodiment of a method of forming a charge pump controller may include configuring no more than three alternately switched switches of the charge pump controller to couple to a capacitor wherein the no more than three alternately switched switches are configured to couple the capacitor in a charging configuration during a first time period and to couple the capacitor to supply a current to an LED during a second time period. Another embodiment of the method may include configuring the charge pump controller to receive a sense signal that is representative of the current and to regulate the current, substantially to a first value.

Regulated charge pump and method therefor

In one embodiment, a circuit is configured to operate with a communication protocol that has at least three different signal levels wherein different sequences of the three levels identify different elements of the communication protocol. In another embodiment, a modular control block may be used to select the communication protocol and the operation of the circuit.

Communication circuit and method therefor

A power amplifier driver ( ) provides control voltage inputs to power amplifier ( ) at terminal (OUT). An output power control loop is implemented through directional coupler ( ) and power amplifier driver ( ). Power amplifier driver ( ) implements a loop integration function utilizing transconductance amplifiers ( ) to convert a detection signal (DET) and a reference signal (REF ) to current for summing at node . Transconductance amplifiers ( ) convert the error voltage generated at node ( ) and bias voltage (V ) to current for summing at node ( ) for subsequent conversion back to voltage by resistor ( ). The error voltage at node ( ) is buffered ( ) to provide adequate current drive at terminal (OUT).

Power amplifier driver and method of using

Problems of noise emission during transmission in successive time slots (A-B) in mobile telephony are solved by causing the transmitted power to change in a monotonic manner from a previous value to a new value. It is shown that this increases the transmission bit rate.

Method of transmitting in successive time slots

High performance audio transmission channel

Voltage regulator ( ) provides current sense comparator ( ) to detect the normal and standby modes of operation for voltage regulator ( ). During a normal mode of operation, current sense comparator ( ) de-asserts signal (MODE), causing voltage regulator ( ) to regulate the output voltage to a predetermined level. Once the current (I ) has diminished below a predetermined value, current sense comparator ( ) asserts signal (MODE) to indicate a standby mode. During the standby mode, regulator ( ) regulates the output voltage (V ) between first and second reference levels, requiring a quiescent current level much less than the quiescent current level required during normal mode, due to the deactivation of current sense comparator ( ) and error amplifier ( ) during standby mode. An alternate method of quiescent current reduction uses switched voltage reference ( ). Bandgap reference ( ) supplies voltage reference (V ) during normal mode of operation and depletion MOS reference supplies voltage reference (V ) during standby mode of operation.

Very low quiescent current regulator and method of using

To reduce the DC-offset in bursts (B B ) of a digital signal (S ), some samples of one of the digital bursts (B ) which have no predetermined value are averaged by an averager (AV) resulting in a correction value (CV). Meanwhile the samples of this digital burst (B ) are temporarily stored in a memory (MEM ). The DC-offset correction value (CV) calculated by the averager (AV) is then substracted from the samples of the digital bursts (B B ). In this way, the dynamic range of the samples is reduced significantly.

Method and circuit arrangement to reduce a DC-offset

A current pulse generator device includes current pulse generator circuits and polarizer circuits. It further includes holding circuits for holding the polarization voltage connected to the generator circuits, the holding circuits connected via switch circuits to the polarizer circuits. The switch circuits can assume in succession a closed or adjustment position in which they connect the holding circuits to the polarizer circuits, and an open or operating position in which they isolate the holding circuits from the polarizer circuits so that the generator circuits generate at least one low-noise current pulse. The device can be used in a phase comparator and a radiocommunication terminal, and the phase comparator can be used in a synthesiser.

Low-noise current pulse generator device

A transmit-receive system includes a phase-locked loop and a translation frequency loop. To bring about frequency hops, the frequencies in the two loops are varied with large increments in opposite directions. It is shown that the noise caused by the frequency division in the loops is thereby reduced.

Transmit-receive system and transmission method, in particular for a

The invention relates to a frequency divider of the type comprising a prescaler followed by a programmable counter, and serving to divide by an overall division ratio D that can be written D=k.N+A. The prescaler operates with a pair of division ratios k/k+1, and includes means for changing from the higher division ratio k+1 to the lower division ratio k as a function of a modulus control signal. N is a first predetermined programmable value corresponding to the division ratio of the programmable counter. A is a second predetermined programmable value such that on being reached by the programmable counter, the prescaler receives the modulus control signal. The following is true: 0.ltoreq.A&lt;N. According to the invention, the prescaler has at least two successive pairs of division ratios p/p+1,p+1/p+2, p+2/p+3, etc., and includes selection means for dynamically selecting one of the pairs as a function of a selection signal, the selected pair constituting the operating pair k/k+1. The selection signal depends on the overall division ratio D that the frequency divider is to apply.

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Lafitte Vigordane, France

Pierre Andre Genest