Tektronix, Inc.

Pierre A Radochonski

Joern B Eriksen

Jerrold J Rogers

Steven F Liepe

Glenn R Johnson

Lawrence Gerald Biggs

John M Kniffin

William W Gellatly

A pixel processor converts data indicating origin, direction, length and intensity of each of a set of lines forming a picture into a half tone bit map on the picture. The pixel processor organizes the picture into an array of similar half tone cells, each half tone cell being a rectangular array of pixels, by storing adjustable data indicating the size of a half tone cell and a pixel intensity threshold level for each pixel of a half tone cell. When processing each line, the pixel processor reads pixel data words out of the bit map, each pixel data word including at least one bit corresponding to a pixel along the path of the line. For each such bit, the pixel processor determines the half tone cell position of the corresponding pixel, determines whether the pixel intensity threshold level assigned to that half tone cell position is lower than the intensity level of the line and sets the state of the bit accordingly. After suitably altering relevant bits of each pixel data word, the pixel processor writes the altered pixel data word back into the bit map memory.

Half toning pixel processor

Stages of a graphics data processing pipeline are interconnected by a common bus for conveying data and arbitration signals to and from each stage. Each data transmitting stage arbitrates for and acquires control of the bus when it has output data to transmit to an addressable storage location within a next stage. Each pipeline stage other than a first stage generates a BUSY bit indicating whether it is processing data or awaiting new input data from its preceding stage. When one pipeline stage has output data to transmit to a next pipeline stage, the transmitting stage periodically polls the receiving stage by acquiring control of the bus and placing on the bus a particular address associated with the next stage. Whenever the next stage detects the presence of the particular address on the bus, it places its BUSY bit on the data lines of the bus. When the sending stage determines from the state of the BUSY bit that the next stage is ready to receive input data, the sending stage acquires control of the bus and sends the input data thereon to the next stage.

Single bus graphics data processing pipeline with decentralized bus

Provided are an apparatus and a method for recording on a recording medium images from a fiber-optic CRT. The apparatus includes a recording medium transport system, control electronics and a first-in, first-out memory. The use of the first-in, first-out memory permits incremental recording which is not limited by relatively long mechanical transport settling times. In operation, N lines of data are input to the memory, line-by-line, as the transport system increments the position of the recording medium and during settling time. When the recording medium has come to rest, these N lines of data are output sequentially from the memory in a first-in, first-out basis, with the CRT incrementing each line vertically on the recording medium for the total of N lines for each increment of the recording medium by the transport system.

Method and apparatus for accelerating the recording rate of a CRT

This invention includes a method and apparatus for causing ink to be ejected from the ink nozzles for a second selected time period if the printer has not functioned for a first selected time period independent of whether power is or is not applied to the printer during those periods. The first time period is selected to minimize the possibility of ink clogging the ink nozzles and the second time period is selected to dislodge any thickened ink which may have developed in the ink nozzle during the first time period. The first time period for most ink compositions and nozzle sizes will be considerably longer than the second time period.

Method and apparatus for avoiding the drying of ink in the ink jets of

A scheme for digitizing a stationary video image is disclosed. The amplitude of a video signal, representing said video image, is sampled at a plurality of points along the time axis and is compared with the count in a counter. If the amplitude equals the count at a particular point on the time axis, the count is stored in a memory in a location corresponding to said particular point. The process is repeated until a count in the counter is stored in said memory in locations corresponding to all of said plurality of points along the time axis of said video signal. If two or more counters are used, each counting from a different initial value, and if two or more corresponding comparators are used to make the above comparison, the time required to digitize said stationary video image may be reduced. Consequently, the time required for the video image to remain stationary is reduced.

Raster scan frame digitizer method and apparatus

An image quality enhancement scheme is disclosed wherein the image information associated with each line of an image source is transferred to one line of an image receiving medium a plurality of times, the quality of the image information transferred to one line of the image receiving medium gradually improving following each subsequent transfer. A fiber optic cathode ray tube (CRT) transfers the image information to the image receiving medium. An electron beam generator in the CRT traces a plurality of scan lines on the inner faceplate of the CRT. The image receiving medium scrolls across the face of the CRT in synchronism with the trace of each of the scan lines on the inner faceplate thereof. The image information associated with each line of the image source is transferred to the one line of the image receiving medium via the trace of each of the plurality of scan lines. Consequently, following each such transfer via the trace of each corresponding scan line, the quality of the image recorded on said one line of the image receiving medium is gradually improved.

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Lake Oswego, OR, United States of America

Pierre A Radochonski