Bull Hn Information Systems Italia S.p.a.

Pierluigi Tagliabue

Roberto Boioli

An interface control circuit includes a shift register which is parallel loaded with a 17 bit binary code and with control information comprising two bits of opposite level loaded in the head cells of the register, the first bit having a control function, the second having a separation function from the 17 bit binary code. The parallel loading is performed by a load command which also sets a control flip flop and wherein a timing circuit, triggered by command, controls in continuous mode the interlocked interface dialogue as long as the control flip flop is set, and causes the register to shift its contents so as to serially unload the binary code to the interface and to serially load the register with the logic level of the control bit, until, at the completion of transferring the control bit level present at a predetermined number of register outputs is inverted, reintroduced in the first register cell and causes the control flip flop to reset and the dialogue to halt. If the binary code transmission has to be followed by the reception of a binary code, the timing unit is held active and the binary code is serially loaded in the register until the control bit, with inverted logic level, appears at a predetermined output of the register and stops the dialogue, the binary code serially loaded in the register being then available for parallel read out.

ESDI interface control circuit

Arbitration circuit operates for common bus access granting where the asynchronous access requests are latched in a register by the rising edge of a periodical square wave timing signal, and from there transferred to a logical priority network, implemented with a programmable logic array.

Growing community of inventors

Milan, Italy

Pierluigi Tagliabue