Radioframe Networks, Inc.

Broadcom Corporation

Pierce Keating

Bill Stevens

Crystal oscillator control and calibration is disclosed. Temperature and frequency control circuits included on a printed circuit board (PCB) comprising a crystal oscillator are used to determine, for each of a plurality of set points in a range of sensed internal temperatures sensed by an internal temperature sensing circuit or device located adjacent to the oscillator in a thermally insulated region of the PCB, a corresponding compensation required to be applied to maintain a desired oscillator output frequency. The PCB is configured to use at least the determined compensation values and a sensed internal temperature to determine during operation of the PCB a compensation, if any, to be applied to maintain the desired oscillator output frequency.

Crystal oscillator temperature control and compensation

A phase locked loop with phase clipping and/or resynchronization is disclosed. A reference signal is compared to a feedback signal derived at least in part from an output signal of an oscillator to determine a phase error. A magnitude of at least one of the phase error and a change in the phase error, if required, is clipped to provide at least one of a clipped phase error that has a clipped magnitude that does not exceed a prescribed maximum phase error and a clipped change in phase error that has a clipped magnitude that does not exceed a prescribed maximum change in phase error. If a resynchronization triggering event is detected, the oscillator is resynchronized with the reference signal.

PLL with phase clipping and resynchronization

Controlling the flow of network traffic to avoid undesired delay in the transmission of timing sensitive packets is disclosed. A plurality of packets to be transmitted via a network transmission path is monitored. A time at which a timing sensitive packet will become available for transmission via the network transmission path is anticipated. The plurality of packets is controlled in light of the anticipated time so that packets other than the timing sensitive packet will not occupy the network transmission path at a time associated with the anticipated time. Approximating a maximum data transmission rate associated with a network transmission path by sending and analyzing receipt of a series of test packets is disclosed. Approximating a buffer size of a buffer associated with a network transmission path by sending and analyzing receipt of a series of test packets is disclosed.

Network delay control

A method and system for processing a signal are disclosed. The method comprises: applying an algorithm to selectively negate a plurality of samples of the signal to provide negated and non-negated samples of the signal, and use the negated and non-negated samples as in-phase (I) and/or quadrature (Q) components of a plurality of complex samples, the algorithm being such that the plurality of complex samples are equivalent to the result that would be obtained by applying an effective sampling function to the signal, and selecting a beat frequency of the effective sampling function by adjusting the algorithm.

Digital undersampling

An oscillator circuit and a method of generating an oscillating signal are disclosed. An oscillator comprises a first flip-flop and a second flip-flop coupled with the first flip-flop to provide an oscillating signal. A method of generating an oscillating signal comprises providing the oscillating signal as a first clock input to a first flip flop, inverting the oscillating signal and providing the inverted oscillating signal as a second clock input to a second flip flop, using the output of the first flip flop and the output of the second flip flop to generate a combined output that alternates between a logic low level and a logic high level, and using the combined output to sustain the oscillation of the oscillating signal.

Clock oscillator

A reference frequency is distributed through a packet-based network to remote elements in a system. Timing packets are periodically sent from a master timing element, to be received by at least one peripheral timing element. Echo messages are sent to the master timing element by each peripheral timing element after a unique delay, in response to the reception of a timing packet. Loopback delay measurements are included in each timing packet for each peripheral timing element. Each peripheral timing element locks a loop using only timing packets which incur a minimum loopback delay.

Growing community of inventors

Issaquah, WA, United States of America

Pierce Keating