International Business Machines Corporation

Pierce I-Jen Chuang

Phillip John Restle

Christos Vezyrtzis

Alper Buyuktosunoglu

Pradip Bose

Giora Biran

Tobias Webel

Preetham M Lobo

Ramon Bertran Monfort

Chia-Yu Chen

Li-Wen Hung

Jui-Hsin Lai

Cheng-Wei Cheng

Seyoung Kim

Kailash Gopalakrishnan

Geoffrey W Burr

Ko-Tao Lee

Jungwook Choi

Pritish Narayanan

HsinYu Tsai

Divya Pathak

Stefano Ambrogio

Zhuo Wang

Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.

Proactive voltage droop reduction and/or mitigation in a processor core

Techniques facilitating voltage management via on-chip sensors are provided. In one example, a computer-implemented method can comprise measuring, by a first processor core, power supply information. The computer-implemented method can also comprise measuring, by the first processor core, a value of an electrical current generated by the first processor core. Further, the computer-implemented method can comprise applying, by the first processor core, a mitigation technique at the first processor core in response to a determination that a combination of the power supply noise information and the value of the electrical current indicates a presence of a voltage noise at the first processor core.

On-chip supply noise voltage reduction or mitigation using local detection loops

Techniques for statistics-aware weight quantization are presented. To facilitate reducing the bit precision of weights, for a set of weights, a quantizer management component can estimate a quantization scale value to apply to a weight as a linear or non-linear function of the mean of a square of a weight value of the weight and the mean of an absolute value of the weight value, wherein the quantization scale value is determined to have a smaller quantization error than all, or at least almost all, other quantization errors associated with other quantization scale values. A quantizer component applies the quantization scale value to symmetrically and/or uniformly quantize weights of a layer of the set of weights to generate quantized weights, the weights being quantized using rounding. The respective quantized weights can be used to facilitate training and inference of a deep learning system.

Statistics-aware weight quantization

Methods and systems for performing calculations with a neural network include determining a conductance drift coefficient for resistive processing unit (RPU) weights in a neural network. A correction factor is applied to neuron inputs in the neural network in accordance with the drift coefficient and a time that has elapsed since the RPU weights were programmed. A calculation is performed with the neural network. The correction factor compensates for conductance drift.

Mitigation of conductance drift in neural network resistive processing units

A voltage droop mitigation system, that includes a first processor core that executes computer executable components stored in a memory. A time-based sensor component generates digital data representing voltage values associated with a power supply. A filtering component digitally conditions the generated digital data, and an analysis component analyzes the conditioned data and determines slope of the power supply voltage and employs counters to determine rate of data change over time; and if the slope is negative and exceeds a first pre-determined value for a pre-determined time period. The system implements one or more voltage droop-reduction techniques at the first processor core; and the first processor core transmits at least one of the following types of information: its voltage value, slope information or decision to apply droop reduction to one or more other cores.

Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors

A method of forming a multi-state nanosheet transistor device is provided. The method includes forming an alternating sequence of sacrificial layer segments and differentially doped nanosheet layer segments on a substrate, wherein each of the differentially doped nanosheet layer segments has a different dopant concentration from the other differentially doped nanosheet layer segments. The method further includes forming a source/drain on each of opposite ends of the sacrificial layer segments and differentially doped nanosheet layer segments, and removing the sacrificial layer segments. The method further includes depositing a gate dielectric layer on the differentially doped nanosheet layer segments, and forming a gate electrode on the gate dielectric layer to form a common gate-all-around structure, where each of the differentially doped nanosheet layer segments conducts current at a different threshold voltage.

Multi-state transistor devices with multiple threshold voltage channels

A random number signal generator used for performing dropout or weight initialization for a node in a neural network. The random number signal generator includes a transistor which generates a random noise signal. The transistor includes a substrate, source and drain regions formed in the substrate, a first insulating layer formed over a channel of the transistor, a first trapping layer formed over the first insulating layer, a second insulating layer formed over the first trapping layer, and a second trapping layer formed over the second insulating layer. One or more traps in the first and second trapping layers are configured to capture or release one or more carriers flowing through the channel region. The random noise signal is generated as a function of one or more carrier being captured or released by the one or more traps.

True random generator (TRNG) in ML accelerators for NN dropout and initialization

Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core

A method, system and computer program product are disclosed that comprise capturing first image data of a person's face using at least one sensor responsive in a band of infrared wavelengths and capturing second image data of the person's face using the at least one sensor responsive in a band of visible wavelengths; extracting image features in the image data and detecting face regions; applying a similarity analysis to image feature edge maps extracted from the first and the second image data; and recognizing a presence of a live face image after regions found in the first image data pass a facial features classifier. Upon recognizing the presence of the live face image, additional operations can include verifying the identity of the person as an authorized person and granting the person access to a resource.

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Briarcliff Manor, NY, United States of America

Pierce I-Jen Chuang