International Business Machines Corporation

Pia Naoko Sanda

Daniel Ray Knebel

Mark Alan Lavin

Prabhakar Nandavar Kudva

Lars W Liebmann

Stanislav Polonsky

Jeffrey Alan Kash

Phillip J Nigh

Steven H Voldman

Pradip Bose

Naresh Nayar

William Vincent Huott

Robert Brett Tremaine

Mark Anthony Check

Jude A Rivers

James Xenidis

John-David Wellman

David P Vallett

Leendert M Huisman

James C Tsang

Richard James Evans

James Lee Van Oosten

Daniel James Henderson

David W Siegel

Harold Wayne Chase

James Chen-Hsiang Tsang

Jamie H Moreno

Xiaodong Xiao

Moyra K Mc Manus

Dennis G Menzer

An attribute of a descriptor associated with a task informs a runtime environment of which instructions a processor is to run to schedule a plurality if resources for completion of the task in accordance with a level of quality of service in a service level agreement.

Tunable error resilience computing

An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault injection test points using a conventional fault injection test verification environment to establish an SER induced failure rate a logic design. The selection method affords a design independent means to evaluate any design regardless of the origin, source language or documentation by working at the common logic device level 'gate-level' netlist format for the design data. The selected set of devices is distilled from the design data by successively filtering the design through a series of heuristic rule-based device identifier computer programs that group and annotate the devices into specific database records. These records are then used to organize the fault injection device test set by test behavior and relevance.

Verification of soft error resilience

Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

Modeling system-level effects of soft errors

A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One embodiment of the invention, utilizes a method such as, but not limited to, time resolved photon emission to observe transistor level switching activity in an integrated circuit (IC).

Method for VLSI system debug and timing analysis

A method and system for visualizing circuit operation. In the method device activity is obtained based on one or more of measured or simulated activity. The device activity is expressed in a representation, and the expressed activity is represented in a visual form. One suitable form of activity is the simulated version of the PICA slow motion movie. The invention may apply to other simulated design data vies as well, such as switch level simulation, current density simulation, and power density simulation.

System and method for VLSI visualization

A system and method for determining the location of a particular device on an integrated circuit chip is described. The system and method utilize apparatus for detecting the emission of light during switching events of devices in the circuit during the circuit's processing of an input calculated to actuate the device whose location is desired. Light emissions from the circuit can be temporally and spatially indexed so as to allow deduction, in combination with the a priori knowledge of the logical operation of the circuit, of the location of the desired element. In another embodiment of the invention, a series of images of the circuit can be accumulated, representing the circuit's response to a series of different input signals, each input signal being designed to result in the switching of the desired element. The series of images can be compared to determine the location of the desired element. Also in accordance with the invention, the elements to be located can be either actual functional circuit elements, or fiducials added to the chip for test purposes.

Using time resolved light emission from VLSI circuit devices for navigation on complex systems

A method is provided for analyzing the functionality of an integrated circuit (IC). The method includes the step of applying a built-in self test (BIST) to the integrated circuit. The BIST includes a plurality of tests that result in the integrated circuit passing and/or failing with respect to predefined criteria. During the applying step, a substrate current of the integrated circuit is measured and analyzed as a function of at least one variable. Also during the applying step, optical emissions of the integrated circuit are measured and analyzed. Defects in the functionality of the integrated circuit are identified, based on at least one of the substrate current and the optical emissions.

Method for IC fault analysis using programmable built-in self test and optical emission

A system and method for identifying long paths in an integrated circuit are described. An integrated circuit chip is subjected to input test signals of progressively shorter cycle time until the chip fails to produce a correct output. The cycle time of the signal resulting in the failure of the chip is defined as T. A signal having cycle time T'=T+.DELTA.T is then applied to the integrated circuit, where the signal of cycle time T' is known to result in proper operation of the chip. The chip is then observed for switching activity during the period .DELTA.T which occurs beginning at a time T measured from the beginning of the second signal of duration T' until the end of the signal of duration T'. The location of the switching activity is used to identify the path or paths of the circuit that resulted in failure of the chip. In a preferred embodiment of the invention, the switching activity is detected using an optical measurement system capable of detecting light generated by transistor switching activity.

Method for identifying long paths in integrated circuits

A system and method to reduce, compress, and analyze the raw data obtained in an apparatus which measures the time-resolved emission of light from an operating integrated circuit is described. The system and method reduce the storage requirements for a tool which measures this emission, and can also reduce the computational time for analysis of the data.

System and method for compressing and analyzing time-resolved optical

An apparatus implemented in a computer aided design (CAD) system automatically generates phase shifted mask designs for very large scale integrated (VLSI) chips from existing circuit design data. The system uses a series of basic geometric operations to design areas requiring phase assignment, resolve conflicting phase assignments, and eliminate unwanted phase edges. This apparatus allows automatic generation of phase shift mask data from any circuit design that allows for phase shifting. Since the dimensional input for all geometric operations is directly linked to the design ground rules given to the circuit designers, any designable circuit layout can also be phase shifted with this algorithm. The autogeneration of phase shift patterns around an existing circuit design is broken down into four major tasks: 1. Define areas that need a phase assignment; 2. Make a first pass phase assignment unique to each critical feature and define 'runs' of interrelated critical features; 3. Propagation phase assignment through the 'runs'; and 4. Design trim features.

Geometric autogeneration of'hard'phase-shift designs for VLSI

A method implemented in a computer aided design (CAD) system automatically generates phase shifted mask designs for very large scale integrated (VLSI) chips from existing circuit design data. The system uses a series of basic geometric operations to design areas requiring phase assignment, resolve conflicting phase assignments, and eliminate unwanted phase edges. This process allows automatic generation of phase shift mask data from any circuit design that allows for phase shifting. Since the dimensional input for all geometric operations is directly linked to the design ground rules given to the circuit designers, any designable circuit layout can also be phase shifted with this algorithm. The autogeneration of phase shift patterns around an existing circuit design is broken down into four major tasks: 1. Define areas that need a phase assignment; 2. Make a first pass phase assignment unique to each critical feature and define 'runs' of interrelated critical features; 3. Propagation phase assignment through the 'runs'; and 4. Design trim features.

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Slingerlands, NY, United States of America

Pia Naoko Sanda