Industrial Technology Research Institute

Pi-Fu Chen

Jr-Hong Chen

Dou-I Chen

Chih-Chiang Chen

Kun-Chih Lin

Chi-Shen Lee

Yuan-Tung Dai

Jeng-Hung Sun

Chung-Shu Chang

Ting-Kuo Chang

Yu-Ming Kang

Wen-Yu Huang

Hsixg-Ju Sung

Wung-Ui Huang

A manufacturing method of a thin film transistor (TFT) having low serial impedance is described. The method uses a back-side exposure and uses the active area as a hard mask; therefore, photomask usage may be reduced. On the other hand, a Si-Ge layer is used to react with the conductive layer deposited thereon after for forming a Ge-salicide layer. The method may reduce the required temperature of forming a Ge-salicide layer and the serial impedance.

Method for manufacturing thin film transistors

A method for fabricating a low temperature polysilicon thin film transistor incorporating a channel passivation step is described. The method achieves dopant ion activation in a polysilicon gate by using laser irradiation, however, with an additional insulating material layer such as SiO or Si N overlying and protecting the channel portion of the polysilicon gate. Any possible contamination by residual photoresist material after a photoresist removal step on the channel portion of the polysilicon gate can thus be avoided. Furthermore, deficiencies such as dopant ions out-diffusion and lateral diffusion can be avoided. The leakage current of the thin film transistors formed by the present invention method is significantly reduced when compared to those formed by a conventional method.

Method for fabricating a low temperature polysilicon thin film transistor incorporating channel passivation step

A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n&plus; amorphous-silicon layer and a metal layer. The metal layer defines a source electrode and a drain electrode. The structure simplifies the photolithography process by using a less number of masks to manufacture thin film transistors. It also reduces the occurrence of open circuits in the first metal (MI) layer or short circuits between the MI layer and the second metal (MII) layer caused by the photoresist residue or particle contamination. The manufacturing method combines a conventional back-channel-etched (BCE) reduced mask process and a two-step exposure technology. The two-step exposure technology uses two photoresist pattern masks. One is a pattern mask for complete exposure with higher light intensity and the other is a pattern mask for incomplete exposure with lower light intensity. The photoresist pattern with incomplete exposure is then etched by an O plasma etching process. The amorphous-silicon layer and the metal layer has the characteristic of an island metal masking structure that protects the active layer from plasma damage in plasma etching process.

Method of manufacturing an amorphous-silicon thin film transistor

Within a method for forming a thin film transistor (TFT) structure, there is first provided a substrate. There is then formed over the substrate a gate electrode. There is then formed adjacent to the gate electrode but not covering a top surface of the gate electrode a backfilling dielectric layer. There is then formed over and covering the top surface of the gate electrode a gate dielectric layer. There is then formed over and covering the gate dielectric layer an active semiconductor layer. Finally, there is then formed over and in electrical communication with the active semiconductor layer a pair of source/drain electrodes, where the pair of source/drain electrodes having a separation distance which defines a channel region of the active semiconductor layer. The method for forming the thin film transistor (TFT) structure contemplates a thin film transistor (TFT) structure fabricated in accord with the method for forming the thin film transistor (TFT) structure. The method provides the thin film transistor (TFT) structure with enhanced functionality and reliability.

Thin film transistor (TFT) structure with planarized gate electrode

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Taipei, Taiwan

Pi-Fu Chen