Industrial Technology Research Institute

Mediatek Corporation

Pi-Cheng Hsiao

Yu-Ming Lin

Jia-Ming Chen

Ya-Ting Chang

Hung-Lin Chou

Tay-Jyi Lin

Chia-Hao Hsu

Yuan-Hua Chu

Gin-Kou Ma

Yun-Ching Li

Chi-Hung Lin

Jen-Chieh Yang

Shih-Yen Chiu

Wan-Ching Huang

Chou-Kun Lin

Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement.

Energy efficiency strategy for interrupt handling in a multi-cluster system

A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

Energy efficient multi-cluster system and its operations

A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a latency prediction unit, and a variable-latency datapath. The adaptive voltage scaling unit generates a plurality of operation voltages and transmits the operation voltages to the variable-latency datapath. The variable-latency datapath operates with different latencies according to the operation voltages and generates an operation latency. The latency prediction unit receives the operation latency and a system latency tolerance and generates a voltage scaling signal for the adaptive voltage scaling unit according to the operation latency and the system latency tolerance. The adaptive voltage scaling unit outputs and scales the operation voltages thereof according to the voltage scaling signal.

Performance scaling device, processor having the same, and performance scaling method thereof

An embodiment of a processing device includes a function unit and a control unit. The function unit receives input data and performs a specific operation to the input data to generate result data. The control unit receives the result data and generates an output signal. The control unit latches the result data according to a first clock signal to generate first data and latches the result data according to a second clock signal to generate second data. The control unit compares the first data with the second data to generate a control signal and selects the first data or the second data to serve as data of the output signal according to the control signal. The second clock signal is delayed from the first clock signal by a predefined time period.

Processing device for determining whether to output a first data using a first clock signal or a second data using delay from the first clock signal according to a control signal

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Taichung, Taiwan

Pi-Cheng Hsiao