International Business Machines Corporation

Other

Phung T Nguyen

Robert C Wong

Ebenezer E Eshun

Nivo Rovedo

Daniel J Jaeger

Thomas A Wallner

David B Colavito

Edward J Nowak

Louis L Hsu

Jeanne P Bickford

Nazmul Habib

Edward P Maciejewski

Chang-Ming Hsieh

Yasuhiro Koike

Lawrence F Wagner, Jr

Karl David Conroy

Bruce Balch

A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa.

Bipolar transistor integrated with metal gate CMOS devices

Method of forming bipolar transistor integrated with metal gate CMOS devices

A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.

One-transistor static random access memory with integrated vertical PNPN device

Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.

Across reticle variation modeling and related reticle

Disclosed is an on-chip test device for testing the thickness of gate oxides in transistors. A ring oscillator provides a ring oscillator output and an inverter receives the ring oscillator output as an input. The inverter is coupled to a gate oxide and the inverter receives different voltages as power supplies. The difference between the voltages provides a measurement of capacitance of the gate oxide. The difference between the voltages is less than or equal to approximately one-third of the difference between a second set of voltages provided to the ring oscillator. The capacitance of the gate oxide comprises the inverse of the frequency of the ring oscillator output multiplied by the difference between the voltages, less a capacitance constant for the test device. This capacitance constant is for the test device alone, and does not include any part of the capacitance of the gate oxide. The measurement of capacitance of the gate oxide is used to determine the thickness of the gate oxide.

Structure for measurement of capacitance of ultra-thin dielectrics

A low cost SRAM (Static Random Access Memory) cell is disclosed with P well and N well contacts and preferably with a P+ diffusion crossing to ground. The SRAM cell is complete at the M2 metal level and has improved cell passgate leakage, functionality and fabrication yields. The SRAM cell comprises cross coupled pnp pull-up devices P, Pand npn pull-down devices N, N, with the P, Pdevices being connected to the power supply VDD, and the N, Ndevices being coupled through a P+ diffusion region to ground. A first passgate is coupled between a first bitline and the junction of the devices Pand N, with its gate coupled to a wordline, and a second passgate is coupled between a second bitline and the junction of devices Pand N, with its gate coupled to the wordline.

SRAM cell with well contacts and P+ diffusion crossing to ground or N+ diffusion crossing to VDD

A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

Method for low topography semiconductor device formation

A charger coupling for charging a battery includes a paddle and a receptacle. The paddle and the receptacle exchange information by radio waves. The paddle includes waveguides for guiding radio waves between an antenna of the paddle and an antenna or the receptacle. The waveguides improve the radio communication between the paddle and the receptacle.

Charger coupling

An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.

Growing community of inventors

Pleasant Valley, NY, United States of America

Phung T Nguyen