Motorola Corporation

Semiconductor Components Industries, LLC

Phuc C Pham

Dwight D Esgar

Paul B Sofianos

Ray D Sundstrom

David K Ford

Philip Alan Jeffery

Harold L Spangler

Gregory A Davis

Carl Denig

Rod J Comer

Lou Spangler

Greg Davis

Hieu Nguyen

John C Veto

Charles B Siragusa

Various embodiments of the present technology comprise a method and apparatus for a continuous time linear equalizer (CTLE). In various embodiments, the CTLE comprises a cross-coupled transistor pair that operates as a negative impedance converter. The CTLE produces a transfer function that provides high gain peaking at a high frequency without increasing the size of the die area and/or the power supply level.

Methods and apparatus for a continuous time linear equalizer

A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.

Method for synchronizing signals and structures therefor

A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.

Non-saturating bipolar transistor circuit

A monolithic shielded integrated circuit is formed using a leadframe (11) having electrically isolated flag areas (12 and 13). Semiconductor die are attached to the electrically isolated flag areas (12 and 13). An integral shield is formed on monolithic integrated circuit (23) for protection against radio frequency noise. A molded package (22) is formed around portions of the leadframe (11) thereby encapsulating the integrated circuit (23) and its integral shield.

Monolithic shielded integrated circuit

A translator circuit (21) converts an ECL logic level to a TTL logic level. The translator circuit (21) operates at high speeds, rejects power supply noise, and does not use Schottky diodes for preventing transistors from saturating. The translator circuit comprises a differential input stage (22), a level shift stage (23), a differential stage (24), and an output stage (25). The differential input stage (22) is responsive to an ECL signal and provides a differential output signal. The level shift stage (23) level shifts the differential output signal of the differential input stage a predetermined DC voltage. The differential stage (24) is responsive to the level shift stage (23) and generates first and second output signals. The differential stage (24) rejects power supply noise coupled from the level shift stage (23). The output stage (25) is responsive to the first and second output signals of the differential stage (24) and converts the first and second signals to a single ended TTL signal corresponding to the logic level of the ECL signal.

ECL to TTL translator with power supply noise suppression

A gain stage for providing an automatic phase shift is provided. In particular, the gain stage detects whether an oscillation signal appears at its inputs. If an oscillation signal is not detected, then the gain stage inverts output signals occurring at outputs of a first amplifier before being respectively applied to inputs of a second amplifier. This has the overall effect of implementing a 180.degree. phase shift of a signal appearing at the outputs of the gain stage with respect to a signal appearing at the inputs of the gain stage.

Saw oscillator gain amplifier with auto phase shift

A temperature compensated voltage regulator circuit having a first resistor (R.sub.X) disposed in the base circuit between two cascaded transistors and a second resistor (R.sub.F) coupled between the collector and base of the first of the two transistors to provide compensation for beta variations in the transistors resulting from process variables during the manufacture of the circuit.

Temperature compensated voltage regulator having beta compensation

A voltage controlled oscillator (VCO) circuit (10) for operating at low supply voltages has been provided. The VCO circuit includes an oscillation stage which utilizes a negative resistance technique for oscillation and includes a first inductor (38) for allowing the oscillation stage to operate at low supply voltages. The VCO circuit also includes an output stage which includes a second inductor (52) and a first capacitor (51) for allowing the output resistance of the VCO circuit to be adjusted for maximum output drive capability.

Voltage controlled oscillator with low operating supply voltage

A voltage controlled oscillator (VCO) circuit having a cascoded output stage has been provided. The VCO circuit includes an oscillation stage which utilizes a negative resistance technique for oscillation, and an output stage that is coupled in cascode with the oscillation stage thereby minimizing the power dissipation and allowing the output resistance of the VCO circuit to be adjusted for maximum drive capability.

Voltage controlled oscillator having cascoded output

An on-chip self-test circuit has been provided that allows for accurately testing a device such as prescaler at high frequencies. The on-chip self-test circuit includes a voltage controlled oscillator for providing high frequency signals to the device under test. The on-chip self-test circuit is rendered active only when one desires to test the device. Thus, when not testing, the on-chip self-test circuit is transparent to the device and consumes substantially zero power.

On-chip self-test circuit

A voltage controlled oscillator circuit including an oscillator circuit having first and second terminals to which an external inductance is connected. A frequency control voltage (V.sub.F) is applied through a bias circuit to the second terminal for varying the center frequency. The oscillator circuit may have an AGC circuit or a modulation circuit connected to it. An output amplifier is connected with the first terminal and has an adjustable output impedance for matching the input impedance of a load circuit.

Voltage controlled oscilator having controlled bias voltage, AGC and

A voltage controlled oscillator circuit has been provided that allows for varying the center frequency of oscillation through an applied voltage signal (V.sub.F). Further, the center frequency of oscillation can be fine tuned around the center frequency via a modulation signal (S.sub.M). The voltage controlled oscillator circuit utilizes a negative resistance technique for oscillation and includes an output amplifier whose output resistance can be adjusted to match the input impedance of another circuit for maximum drive capability.

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Chandler, AZ, United States of America

Phuc C Pham