Texas Instruments Corporation

Philomena Cleopha Brady

Ananthakrishnan Viswanathan

Joseph Michael Leisten

Brent Alan McDonald

Salvatore Giombanco

Harish Venkataraman

Erick Omar Torres

Shanguang Xu

Sombuddha Chakraborty

Laszlo Balogh

William E Grose

Vikram Joseph Mani

Nakshatra S Gajbhiye

Eric Southard

Teuta K Williams

David Thomas Bailey

Bala Krishnan D Achie

Saad Pervaiz

A controller for a boost power factor correction (PFC) converter. The controller is configured to operate the boost PFC converter in multiple operating modes, including a continuous conduction mode (CCM), a transition mode (TM), and a hybrid mode in which the controller operates the converter in both CCM and TM within a same line cycle. An example controller includes a current control loop and a mode transition circuit. The current control loop is configured to compute an inductor current for each of first and second operation modes, based on a current sample taken, for example, during a boost synchronous rectifier conduction period of the converter. The mode transition circuit includes digital logic circuitry and is configured to generate a pulse indicating that one, two or all three of: zero-voltage switching (ZVS) has been achieved; the synchronous rectifier conduction period is active; and/or one of TM or hybrid mode is active.

Autonomous mode transition for multimode operation in boost PFC converters

A switching converter is provided that includes a power MOSFET, a controller having a drive pin connected to a gate terminal of the power MOSFET, and a resistor connected to the gate terminal. A compensation time selection circuit is included that has compensation times stored therein. A compensation time is selected from the compensation times based on a value of the resistor and stored in the controller. The selected compensation time compensates for an inherent delay in switching the power MOSFET to an ON state after the power MOSFET receives a signal to switch to the ON state to allow the power MOSFET to switch to the ON state when a drain voltage of the power MOSFET's reaches its lowest value during a switching cycle.

System for programming a compensation time into a switching converter

A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Zero current and valley detection for power factor correction

An inductor conducts a first current, which is variable. A first transistor is coupled through the inductor to an output node. The first transistor alternately switches on and off in response to a voltage signal, so that the first current is: enhanced while the first transistor is switched on in response to the voltage signal; and limited while the first transistor is switched off in response to the voltage signal. A second transistor is coupled to the first transistor. The second transistor conducts a second current, which is variable. On/off switching of the second transistor is independent of the voltage signal. Control circuitry senses the second current and adjusts the voltage signal to alternately switch the first transistor on and off in response to: the sensing of the second current; and a voltage of the output node.

Method and circuitry for sensing and controlling a current

Programmable switching converter

A Power Factor Correction (PFC) controller includes an error amplifier for amplifying a difference between Vout and intended Vout to provide a power demand (Pdem) output at a compensation pin. A burst mode controller includes soft-start circuitry coupled to receive Pdem and to a drive pin which provides pulses to a control node of a power switch of a DC-DC converter during burst periods. The pulses slow ramping of line current over a first 2 to 36 switching cycles at a beginning of bursts when energizing the inductor to reduce a line current slope as compared to without ramping up, and for slowing ramping down of line current over the last 2 to 36 switching cycles to reduce a line current slope when de-energizing the inductor as compared to a line current without ramping down. The PFC controller does not utilize zero-crossings of the line voltage for burst period synchronization.

PFC controller providing reduced line current slope when in burst mode

Disclosed examples include methods and control circuits to operate a single or multi-phase DC-DC converter, including an output that turns a first switch on for a controlled on time and then turns the switch off for a controlled off time in successive control cycles, as well as a PWM circuit that computes a threshold time value corresponding to a predetermined peak inductor current and a duty cycle value, and computes a first time value according to an error value for a subsequent second switching control cycle. The PWM circuit sets the on time to the first time value to operate in a critical conduction mode for the second switching control cycle when the first time value is greater than or equal to the threshold time value, and otherwise sets the controlled on time to the threshold time value for discontinuous conduction mode operation in the second control cycle.

Single and multi-phase DC-DC converter mode control

A power delivery and control device that includes a voltage input line, a voltage output line, a control logic unit coupled to the voltage input and voltage output line to control a voltage being delivered by the voltage output line based on a programmable behavior parameter, a voltage output register accessible to the control logic unit to define the programmable behavior parameter, a control register accessible to the control logic unit to activate and deactivate the voltage output line, and a control line coupled to the control logic unit to receive commands to change content of the voltage output register.

Programmable and simultaneous load switch control for power sequencing

Anti-lock and intelligent braking systems have become ubiquitous in modern vehicles, which employ wheel speed sensors or WSSs. These WSSs generally uses current-domain signals (transmitted through power wires) to reduce the size of the vehicle's wiring harness, but because a vehicle is an inherently noisy environment, mixed signal circuit or MSC (used to decode these signals for a microcontroller) should be able to filter out or compensate for noise. However, traditional MSCs have been plagued with problems, partly due to errors in time base measurement due to noise (as well as other factors). Here, an MSC is provided that accurately calculates a wheel speed pulse width (which is used for time base measurements) by observing the wheel speed pulse as it passes through several thresholds.

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Corinth, TX, United States of America

Philomena Cleopha Brady