Sperry Rand Corporation

Phillip W Marsh

Gregory B Wiedenman

A buffer memory arrangement for use in conjunction with a controller and a plurality of peripheral units and/or subsystems of a data processing system. The arrangement includes a dynamic RAM buffer memory for receiving and storing information from the peripheral units or subsystems and for supplying stored information to such units, an address pointer memory for storing buffer memory addresses identifying locations in buffer memory from which information is to be read or into which information is to be stored, and an encoder responsive to a request signal from a peripheral unit or subsystem for supplying an identity signal to the address pointer memory, which signal identifies the requesting peripheral unit or subsystem and specifies location in the address pointer memory containing buffer memory addresses which are to be applied to the buffer memory. Upon designating the location in buffer memory from which information is to be read or into which information is to be stored, the identified peripheral unit or subsystem signals the buffer memory to indicate that information is to be read or written; then, if information is to be written into the buffer memory, such information is supplied by the peripheral unit, and if information is to be read from the buffer memory, the buffer memory supplies such information to the requesting unit or subsystem.

Buffer memory arrangement

In a throughput error detection system, a redundant logic unit is provided along with a required logic unit for simultaneous operation therewith. The required logic unit and redundant logic unit both produce output data which, it is desired, will be the same. The output data from the required logic unit is supplied to a data bus and the output data of the redundant logic unit is supplied to a parity check digit generator. From the data received from the redundant logic unit, the parity check digit generator generates a parity check digit which is applied to the data bus along wih the data from the required logic unit. A parity checking circuit receives the data and the parity check digit from the data bus and a calculation is made by the circuit to determine if parity is correct. If parity is not correct, the checking circuit produces an alarm signal to alert a user.

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Granger, UT, United States of America

Phillip W Marsh