Cirrus Logic Inc.

Silicon Laboratories Inc.

St-ericsson Sa

Nxp B.v.

Other

Crystal Semiconductor Corporation

Phillip Matthews

Frederick Rush

G Diwakar Vishakhadatta

Jeff Klaas

Ronald D Malcolm

Mark Gentry

Kenneth Wilson Fernald

Thomas Saroshan David

John M Khoury

Xue-Mei Gong

Paul Zavalney

Shaojie Chen

Jing Liang

Gannavaram Diwakar Vishakhadatta

Karma S Bhutia

Systems and methods are disclosed for spur mitigation for pulse signal drivers in radio frequency (RF) devices. An RF integrated circuit includes RF circuitry and analog-to-digital (ADC) circuitry. The RF circuitry operates using a local oscillator (LO) clock to receive and/or transmit RF signals, and the ADC circuitry samples one or more analog input signals and has internal timing based upon a raw digital clock. A retime circuit receives the raw digital clock and the LO clock and has a retimed clock as an output. The retimed clock represents the raw digital clock retimed with the LO clock. While other digital circuitry is timed using the raw digital clock, one or more drivers are timed by the retimed clock and provide pulse output signals to output pads. Having the drivers timed with the retimed clock and other digital circuitry timed with the raw digital clock improves overall performance.

Spur mitigation for pulse output drivers in radio frequency (RF) devices

A system for communicating information includes one device that communicates information via a communication link. The system also includes a second device to communicate information via the communication link. The second device includes a receiver to receive information from the communication link. The second device also includes an oscillator that provides at least one timing signal to the receiver. The oscillator is disabled when the communication link is in an idle state. The oscillator is enabled when the communication link is in a non-idle state.

Communication apparatus having an oscillator that is disabled based on idle state detection of a communication link and associated methods

An apparatus includes a detector to detect an idle state of a communication link that communicates bursts or packets of information. The apparatus also includes an oscillator having low-power and normal modes of operation. The oscillator makes a transition to the low-power mode during the idle state of the communication link. The oscillator leaves the low-power mode of operation and enters the normal mode of operation when the communication link is in a non-idle state.

Low-power communication apparatus and associated methods

A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

Communication apparatus implementing time domain isolation with restricted bus access

A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.

Apparatus using interrupts for controlling a processor for radio isolation and associated method

Method of controlling a processor for radio isolation using a timer

A wireless communication system is provided that includes RF circuitry and signal processing circuitry. The signal processing circuitry includes a dedicated frequency burst (FB) search hardware circuit which exhibits relatively low noise in comparison with other digital processing circuitry, such as a DSP and MCU, within the system. The RF circuitry, dedicated FB search hardware circuit and the other digital processing circuitry can each be activated and inactivated. In one embodiment, when the RF circuitry and the dedicated FB search hardware are active, other digital processing circuitry remains inactive to avoid noise problems that could degrade reception and interfere with the FB search hardware locating the FB. Noise problems in the system are thus desirably reduced.

Wireless communication system with hardware-based frequency burst detection

Apparatus for controlling a digital signal processor for radio isolation and associated methods

A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a first timing circuit that provides timed signals to control timing of system operations during an active mode of operation of the digital processing circuit, and a second timing circuit that provides timing signals to control timing of system operations during an active mode of operation of the radio frequency circuit. In one particular embodiment, at least a portion of the first timing circuit is disabled when the radio frequency circuit is active (receiving and/or transmitting).

Communication apparatus including dual timer units

A single chip audio systemincludes a bus interfacedigital to analog convertersan analog mixerand analog spatial enhancement circuitryDigital to analog convertersconvert digital audio data received through bus interfaceinto analog signals. Analog mixermixes signals received from digital to analog converterswith an analog signal received from an external source. Analog spatial enhancement circuitryenhances first and second mixed analog signals output from analog mixer

Single-chip audio circuits, methods, and systems using the same

An audio system includes circuitry for generating an audio data stream and circuitry for generating digital words defining a volume control level. System also includes volume control circuitry for controlling the amplitude of the audio data stream in response to the digital words. Volume control circuitry includes a master register for holding digital words received from circuitry for generating and a slave register for holding a digital word selectively transferred from master register in response to an enable signal. Output control circuitry and receive the audio data stream and apply a preselected gain defined by the digital word held in slave register . Volume control circuitry also includes circuitry for generating the enable signal when a digital word held in the master register changes and the audio data stream output from ouput control circuitry reaches a zero crossing.

Single-chip audio system volume control circuitry and methods

Amplitude control circuitry includes a first register for storing received amplitude control data and a second register for storing amplitude control data transfered from first register . Output circuitry controls the amplitude of a received signal in response to amplitude data transferred from second register. A sensor determines when data stored in first register and second register does not match and enables a comparator when data in first register and, second register does not match. Comparator compares a signal output from output circuitry with a reference signal and generates a signal for enabling the transfer of data from first register to second register when the signal output from output circuitry falls within a window defined by the reference voltage.

Signal amplitude control circuitry and methods

A single chip audio system includes a bus interface , digital to analog converters , an analog mixer , and analog spatial enhancement circuitry . Digital to analog converters convert digital audio data received through bus interface into analog signals. Analog mixer mixes signals received from digital to analog converters with an analog signal received from an external source. Analog spatial enhancement circuitry enhances first and second mixed analog signals output from analog mixer

Single-chip audio circuitry, method, and systems using the same

An audio system,includes digital-to-analog converters,having left and right paths for converting received left and right streams of digital audio data and a plurality of analog data ports for receiving left and right channel streams of analog audio data. Mixer,has left and right paths for selectively mixing left and right channel data passed from converters,and left and right channel data passed from the analog data ports. Muting circuitry is also provided for selectively muting said right and left channel data to be passed to mixer,from converters,. Circuitry is also included for idling a selected one of the left and right paths of mixer,when selected data path to mixer,is muted.

Growing community of inventors

Austin, TX, United States of America

Phillip Matthews