Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Qualcomm Incorporated

Compaq Information Technologies Group, L.p.

Phillip M Jones

Robert A Lester

Gary J Piccirillo

Kenneth T Chin

Michael J Collins

Jerome J Johnson

Ronald Timothy Horan

Gregory N Santos

Clarence K Coffee

Robert C Elliott

Paul B Rawlins

John Edward Larson

Suresh Kumar Venkumahanti

Jeffrey C Stevens

C Kevin Coffee

Sompong Paul Olarig

Lucian Codrescu

John Erven Jenne

William J Walker

Jiajin Tu

Erich Plondke

Peter K Lee

William C Anderson

Kourosh Gharachorloo

Kenneth A Jansen

Muhammad Ahmed

Jeff W Wolford

Jens K Ramsey

Paras A Shah

Robert Allan Lester

James K Yu

Robert L Woods

Clarence Coffee

Stephen Robert Shannon

Lin Wang

Robert C Elliot

Daisy T Palal

Jeff Stevens

Vasileios Balabanos

Andrew D Olsen

James Andre

Jim Blocker

A method includes receiving an instruction to be executed by a processor. The method further includes performing a lookup in a page crossing buffer that includes one or more entries to determine if the instruction has an entry in the page crossing buffer. Each of the entries includes a physical address. The method further includes, when the page crossing buffer has the entry in the page crossing buffer, retrieving a particular physical address from the entry in the page crossing buffer.

Speculative addressing using a virtual address-to-physical address page crossing buffer

Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

Bimodal branch predictor encoded in a branch instruction

A system comprises a plurality of nodes coupled together via a switching device. Each node comprises a processor coupled to a memory. Migration logic in the switching device is configured to migrate segments of each memory to the switching device.

Method and system for migrating memory segments

A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction.

System and method of using an N-way cache

An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

Multi-mode instruction memory unit

Method and apparatus for reducing castouts in a snoop filter. More specifically, there is provided a system comprising a plurality of buses, one or more processors coupled to each of the plurality of buses and a snoop filter. The snoop filter configured to eliminate unnecessary snoops of the plurality of buses, and further configured to track requests from the one or more processors only if tracking the request does not result in a castout penalty.

Techniques for reducing castouts in a snoop filter

Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

Technique for improving processor performance

Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.

Method for improving processor performance

A cache-based system is adapted for dynamic cache partitioning. A cache is partitioned into a plurality of cache partitions for a plurality of entities. Each cache partition can be assigned as a private cache for a different entity. If a first cache partition satisfying a first predetermined cache partition condition and a second cache partition satisfying a second predetermined cache partition condition are detected, then the size of the first cache partition is increased by a predetermined segment and the size of the second cache partition is decreased by the predetermined segment. An entity can perform cacheline replacement exclusively in its assigned cache partition, and also be capable of reading any cache partition.

Dynamic cache partitioning

A computer system including multiple CPUs inform other logic in a computer system as to the priority level (e.g., task priority) associated with the CPU or software executing thereon. The logic makes arbitration decisions regarding CPU transactions based, at least in part, on the task priorities of the various CPUs. The logic that implements this technique may be a host bridge within a computer system having multiple CPUs or in a switch or router that interconnects multiple nodes or computer systems.

Arbitration technique based on processor task priority

A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.

Next snoop predictor in a host controller

A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.

Coherency control module for maintaining cache coherency in a multi-processor-bus system

A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming &ldquo;memory-starved.&rdquo; Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.

Computer system with adaptive memory arbitration scheme

An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.

System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops

Growing community of inventors

Spring, TX, United States of America

Phillip M Jones